公开(公告)号：US09343119B2

公开(公告)日：2016-05-17

申请号：US14479020

申请日：2014-09-05

Applicant: Intel Corporation

Inventor： Nicolas L. Irizarry ,  Balaji Srinivasan

IPC: G11C7/22 ,  G11C5/14 ,  G11C13/00 ,  G11C16/30

CPC classification number: G11C5/147 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C16/30

Abstract: Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed.

Abstract translation: 总线电路和相关技术的实施例在此公开。 在一些实施例中，总线电路可以包括：源极跟随器布置，包括耦合在电源电压和存储器单元的存取线之间的第一晶体管和第二晶体管，其中第一晶体管和第二晶体管各自具有栅极 并且其中所述访问线是位线或字线; 电容器，其具有耦合到所述第一晶体管的栅极端子并具有耦合到参考电压的第二端子的第一端子; 以及耦合在电容器的第一端子和电压调节器之间的开关。 可以公开和/或要求保护其他实施例。

公开(公告)号：US12062410B2

公开(公告)日：2024-08-13

申请号：US17114407

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Ashraf B. Islam ,  Jaydip Bharatkumar Patel ,  Yasir Mohsin Husain ,  Balaji Srinivasan ,  Nicolas L. Irizarry

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.

公开(公告)号：US20220270680A1

公开(公告)日：2022-08-25

申请号：US17184462

申请日：2021-02-24

Applicant: Intel Corporation

Inventor： Noble Narku-Tetteh ,  Yasir Mohsin Husain ,  Ripudaman Singh ,  Nicolas L. Irizarry

IPC: G11C13/00

Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.

公开(公告)号：US12154623B2

公开(公告)日：2024-11-26

申请号：US17184462

申请日：2021-02-24

Applicant: Intel Corporation

Inventor： Noble Narku-Tetteh ,  Yasir Mohsin Husain ,  Ripudaman Singh ,  Nicolas L. Irizarry

IPC: G11C13/00

Abstract: Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.

公开(公告)号：US20220180905A1

公开(公告)日：2022-06-09

申请号：US17114407

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Ashraf B. Islam ,  Jaydip Bharatkumar Patel ,  Yasir Mohsin Husain ,  Balaji Srinivasan ,  Nicolas L. Irizarry

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C7/14 ,  G11C8/08

Abstract: A method, apparatus and system. The method includes: generating a feedback voltage VFB in a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vvdm at said one of the BL or WL; generating, in a reference circuit, one of a reference voltage VREF to track a feedback voltage of the feedback circuit or a mirror current IMFBmirror to track a current Icell through said each of the memory cells; and providing one of values for both VFB and VREF, or for an output voltage Vapsout corresponding to IMFBmirror, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of VFB with VREF or based on Vapsout.