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公开(公告)号：US20200083155A1
公开(公告)日：2020-03-12
申请号：US16128284
申请日：2018-09-11
Applicant: Intel Corporation
Inventor： Raul ENRIQUEZ SHIBAYAMA , Vijaya BODDU , Luis Nathan PEREZ ACOSTA , Francisco Javier GALARZA MEDINA , Kai XIAO , Luis ROSALES-GALVAN , Beom-Taek LEE , Carlos Alberto LIZALDE MORENO , Gaudencio HERNANDEZ SOSA , Mo LIU
IPC: H01L23/498 , H05K1/02 , H05K1/11
Abstract: Apparatuses, systems and methods associated with electrical routing layout of printed circuit boards and integrated circuit substrates are disclosed herein. In embodiments, an apparatus includes a first electrically conductive path that extends through a region, wherein the first electrically conductive path includes a first pad located at a surface of the region, a first via that extends through the region, and a first trace that extends in a first direction. The apparatus further includes a second electrically conductive path that extends through the region, wherein the second electrically conductive path includes a second pad located at the surface and adjacent to the first pad, a second via that extends through the region, and a second trace that extends in a second direction. Other embodiments may be described and/or claimed.
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Patent Agency Ranking
公开(公告)号：US20210289617A1
公开(公告)日：2021-09-16
申请号：US17333723
申请日：2021-05-28
Applicant: Intel Corporation
Inventor： Richard I. MELLITZ , Brandon GORE , Beom-Taek LEE
Abstract: Methods and apparatus to facilitate routing of high-speed data channels are described herein. Under one aspect, a high-speed data channel is routed between an integrated circuit (IC) and a high-speed data connector mounted to a multilayer printed circuit board as part of a circuit assembly. The circuit assembly includes a signal pathway providing a high-speed data channel from the integrated circuit to the high-speed data connector, wherein a portion of the signal pathway includes an axial cable, such as a twin axial cable. The high-speed data channel may comprise a multi-lane data channel and may be bi-directional.
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公开(公告)号：US20190044286A1
公开(公告)日：2019-02-07
申请号：US16134759
申请日：2018-09-18
Applicant: Intel Corporation
Inventor： Se-Jung MOON , Hansel DSILVA , Beom-Taek LEE
IPC: H01R13/6471 , H01R13/652
Abstract: In accordance with embodiments disclosed herein, there is provided a ground bar as a robust grounding scheme for a high-speed connector design. A connector includes a housing and a first signal pin, first and second ground pins, and a ground bar disposed within the housing. The housing includes a first receptacle through which a first circuit board is inserted. Responsive to the first circuit board being inserted into the first receptacle, the first signal pin is to contact a first contact electrode on the first circuit board, the first ground pin is to contact a first ground contact electrode on the first circuit board, and the second ground pin is to contact a second ground contact electrode on the first circuit board. The ground bar is connected between a first connection point of the first ground pin and a second connection point of the second ground pin.
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公开(公告)号：US20210159625A1
公开(公告)日：2021-05-27
申请号：US16857833
申请日：2020-04-24
Applicant: Intel Corporation
Inventor： Se-Jung MOON , Chien-Ping KAO , Gaudencio HERNANDEZ SOSA , Beom-Taek LEE
Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.
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公开(公告)号：US20190200450A1
公开(公告)日：2019-06-27
申请号：US16328412
申请日：2017-09-19
Applicant: Intel Corporation
Inventor： Richard I. MELLITZ , Brandon GORE , Beom-Taek LEE
CPC classification number: H05K1/0243 , H01L23/66 , H01R12/716 , H05K1/028 , H05K1/0298 , H05K1/112 , H05K1/144 , H05K1/181 , H05K2201/042 , H05K2201/10189 , H05K2201/10356 , H05K2201/10378 , H05K2201/10734
Abstract: Methods and apparatus for utilizing flexible (flex) circuit technology and/or axial cable to facilitate routing of high-speed data channels are described herein. Under one aspect, a high-speed data channel if routed between an integrated circuit (IC) and a high-speed data connector mounted to a multilayer printed circuit board as part of a circuit assembly. The circuit assembly includes a signal pathway providing a high-speed data channel from the integrated circuit to the high-speed data connector, wherein a portion of the signal pathway includes a flex circuit or axial cable.
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公开(公告)号：US20160134036A1
公开(公告)日：2016-05-12
申请号：US14539597
申请日：2014-11-12
Applicant: Intel Corporation
Inventor： Shaowu HUANG , Ifiok J. UMOH , Kai XIAO , Beom-Taek LEE
IPC: H01R12/70
CPC classification number: G06F13/4086
Abstract: A channel (e.g., memory channel) coupling a processor to multiple devices (e.g., DIMMs) is described. The channel has an interconnect topology with multiple interconnect portions coupled together with two or more junctions. At least one of these junctions has first and second interconnect portions that cross each other to form a plus-shaped junction. Also, the interconnect routing between the two or more junctions has an impedance matched to impedance of the two or more junctions.
Abstract translation: 描述了将处理器耦合到多个设备（例如，DIMM）的通道（例如，存储器通道）。 该通道具有互连拓扑，其中多个互连部分与两个或更多个结连接在一起。 这些结中的至少一个具有相互交叉以形成正形结的第一和第二互连部分。 而且，两个或多个结之间的互连布线具有与两个或多个结的阻抗匹配的阻抗。
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