公开(公告)号：US20200250028A1

公开(公告)日：2020-08-06

申请号：US16267323

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Naveen Prabhu VITTAL PRABHU ,  Bharat M. PATHAK ,  Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE ,  Violante MOSCHIANO ,  Walter DI FRANCESCO ,  Michele INCARNATI ,  Antonino Giuseppe LA SPINA

IPC: G06F11/10 ,  G11C29/44 ,  G11C29/52 ,  G11C16/10 ,  G11C11/56 ,  G06F11/07

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

公开(公告)号：US20200090743A1

公开(公告)日：2020-03-19

申请号：US16593868

申请日：2019-10-04

Applicant: Intel Corporation

Inventor： Aliasgar S. MADRASWALA ,  Bharat M. PATHAK ,  Binh N. NGO ,  Naveen VITTAL PRABHU ,  Karthikeyan RAMAMURTHI ,  Pranav KALAVADE

IPC: G11C11/56 ,  G11C8/08 ,  G11C16/26 ,  G11C16/08

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

公开(公告)号：US20190227751A1

公开(公告)日：2019-07-25

申请号：US16370743

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Xin GUO ,  Aliasgar S. MADRASWALA ,  Bharat M. PATHAK

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/10

Abstract: A memory device is designed to store data in multilevel storage cells (MLC storage cells). The memory device includes a controller that dynamically writes data to the storage cells according to a first MLC density or a second MLC density. The second density is less dense than the first density. For example, the controller can determine to use the first density when there is sufficient write bandwidth to program the storage cells at the first density. When the write throughput increases, the controller can program the same MLC storage cells at the second density instead of the first density, using the same program process and voltage.