公开(公告)号：US20250105095A1

公开(公告)日：2025-03-27

申请号：US18471356

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Bozidar Marinkovic ,  Benjamin Kriegel ,  Payam Amin ,  Dolly Natalia Ruiz Amador ,  Thomas Jacroux ,  Makram Abd El Qader ,  Tofizur RAHMAN ,  Xiandong Yang ,  Conor P. Puls

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528

Abstract: An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between the end sections. One or both end sections are wider than the body section, e.g., by approximately 6 nanometers to approximately 12 nanometers. One end section is connected to an interconnect at the backside of the support structure. The other end section is connected to a jumper, which is connected to the source electrode or drain electrode.

公开(公告)号：US20250140748A1

公开(公告)日：2025-05-01

申请号：US18498519

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： Payam Amin ,  Mandip Sibakoti ,  Bozidar Marinkovic ,  Tofizur RAHMAN ,  Conor P. Puls

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more conductive vias is described herein. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, a resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, wherein the third portion is between the first portion and the second portion, and the third width is smaller than the first width and the second width. In one such example, the conductive via tapers from both ends towards the third portion between the ends.

公开(公告)号：US20250132245A1

公开(公告)日：2025-04-24

申请号：US18491111

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Conor P. Puls ,  Payam Amin ,  Santhosh Koduri ,  Clay Mortensen ,  Bozidar Marinkovic ,  Shivani Falgun Patel ,  Richard Bonsu ,  Jaladhi Mehta ,  Dincer Unluer

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.