公开(公告)号：US20230369508A1

公开(公告)日：2023-11-16

申请号：US17742644

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Timothy Jen ,  Prem Chanani ,  Cheng Tan ,  Brian Wadsworth ,  Andre Baran ,  James Pellegren ,  Christopher J. Wiegand ,  Van H. Le ,  Abhishek Anil Sharma ,  Shailesh Kumar Madisetti ,  Xiaojun Weng

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/78687 ,  H01L23/5283 ,  H01L29/7869 ,  H01L27/10814

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.

公开(公告)号：US20230369509A1

公开(公告)日：2023-11-16

申请号：US17742638

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Jisoo Kim ,  Xiaoye Qin ,  Timothy Jen ,  Harish Ganapathy ,  Van H. Le ,  Huiying Liu ,  Prem Chanani ,  Cheng Tan ,  Shailesh Kumar Madisetti ,  Abhishek Anil Sharma ,  Brian Wadsworth ,  Vishak Venkatraman ,  Andre Baran

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/7869 ,  H01L23/5283 ,  H01L27/10814

Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.