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公开(公告)号：US11062752B2
公开(公告)日：2021-07-13
申请号：US16246358
申请日：2019-01-11
Applicant: Intel Corporation
Inventor： Tofizur Rahman , James Pellegren , Angeline Smith , Christopher Wiegand , Noriyuki Sato , Tanay Gosavi , Sasikanth Manipatruni , Kaan Oguz , Kevin O'Brien , Benjamin Buford , Ian Young
Abstract: A perpendicular spin orbit torque memory device includes a first electrode having tungsten and at least one of nitrogen or oxygen and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first magnet, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
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公开(公告)号：US20200227104A1
公开(公告)日：2020-07-16
申请号：US16246358
申请日：2019-01-11
Applicant: Intel Corporation
Inventor： Tofizur Rahman , James Pellegren , Angeline Smith , Christopher Wiegand , Noriyuki Sato , Tanay Gosavi , Sasikanth Manipatruni , Kaan Oguz , Kevin O'Brien , Benjamin Buford , Ian Young
Abstract: A perpendicular spin orbit torque memory device includes a first electrode having tungsten and at least one of nitrogen or oxygen and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first magnet, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
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公开(公告)号：US11276730B2
公开(公告)日：2022-03-15
申请号：US16246360
申请日：2019-01-11
Applicant: Intel Corporation
Inventor： Kevin O'Brien , Christopher Wiegand , Tofizur Rahman , Noriyuki Sato , Gary Allen , James Pellegren , Angeline Smith , Tanay Gosavi , Sasikanth Manipatruni , Kaan Oguz , Benjamin Buford , Ian Young
Abstract: A perpendicular spin orbit memory device includes a first electrode having a magnetic material and platinum and a material layer stack on a portion of the first electrode. The material layer stack includes a free magnet, a fixed magnet above the first electrode, a tunnel barrier between the free magnet and the fixed magnet and a second electrode coupled with the fixed magnet.
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公开(公告)号：US10943950B2
公开(公告)日：2021-03-09
申请号：US16367126
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Michael Robinson , Huiying Liu
Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.
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5.发明申请公开(公告)号：US20200312907A1
公开(公告)日：2020-10-01
申请号：US16367126
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Michael Robinson , Huiying Liu
Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.
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Patent Agency Ranking
公开(公告)号：US11737368B2
公开(公告)日：2023-08-22
申请号：US16367136
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Michael Robinson , Huiying Liu
Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.
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公开(公告)号：US11063088B2
公开(公告)日：2021-07-13
申请号：US16706470
申请日：2019-12-06
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Juan G. Alzate-Vinasco , Yu-Jin Chen , Tanmoy Pramanik
Abstract: A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.
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公开(公告)号：US20210175284A1
公开(公告)日：2021-06-10
申请号：US16706470
申请日：2019-12-06
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Juan G. Alzate-Vinasco , Yu-Jin Chen , Tanmoy Pramanik
Abstract: A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.
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公开(公告)号：US20230369508A1
公开(公告)日：2023-11-16
申请号：US17742644
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Timothy Jen , Prem Chanani , Cheng Tan , Brian Wadsworth , Andre Baran , James Pellegren , Christopher J. Wiegand , Van H. Le , Abhishek Anil Sharma , Shailesh Kumar Madisetti , Xiaojun Weng
IPC: H01L29/786 , H01L23/528 , H01L27/108
CPC classification number: H01L29/78687 , H01L23/5283 , H01L29/7869 , H01L27/10814
Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.
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公开(公告)号：US20230369340A1
公开(公告)日：2023-11-16
申请号：US17742651
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Van H. Le , Timothy Jen , Vishak Venkatraman , Shailesh Kumar Madisetti , Cheng Tan , Harish Ganapathy , James Pellegren , Kamal H. Baloch , Abhishek Anil Sharma
IPC: H01L27/12 , H01L29/786 , H01L23/528 , H01L27/108
CPC classification number: H01L27/1225 , H01L29/7869 , H01L23/5283 , H01L27/1255 , H01L27/10805
Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.
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