公开(公告)号：US20160075551A1

公开(公告)日：2016-03-17

申请号：US14949470

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： RAJASHREE BASKARAN ,  CHRISTOPHER M. PELTO

IPC: B81B7/00 ,  B81B3/00

CPC classification number: B81B7/0006 ,  B81B3/0021 ,  B81B7/02 ,  B81C1/00246 ,  B81C2203/0771 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L29/84 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.

Abstract translation: 一种集成电路器件，其包括单个半导体衬底，形成在单个半导体衬底的前侧上的器件层，形成在单个半导体衬底的背面上的再分配层，形成在单个半导体衬底内的贯通硅通孔（TSV） 其被电耦合到器件层和再分配层，形成在单个半导体衬底的背面上的逻辑存储器接口（LMI），该逻辑存储器接口电耦合到再分配层;以及MEMS器件，其形成在 电耦合到再分布层的单个半导体衬底。