公开(公告)号：US20180005496A1

公开(公告)日：2018-01-04

申请号：US15201205

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： GEORGIOS C. DOGIAMIS ,  RAJASHREE BASKARAN

IPC: G08B6/00 ,  G06F3/01 ,  G06F1/16

CPC classification number: G08B6/00 ,  G04C3/001 ,  G04G21/00 ,  G06F1/163 ,  G06F3/016

Abstract: A wearable electronic device includes a displaceable member communicably coupled to a haptic control circuit. The haptic control circuit is communicably coupled to a configurable haptic output device. A user input, received at the displaceable member generates an input signal that includes information and/or data indicative of at least one displacement parameter associated with the displacement of the displaceable member. The input signal is communicated to the haptic control circuit. The haptic control circuit determines a haptic output parameter that corresponds to the received displacement parameter.

公开(公告)号：US20160233206A1

公开(公告)日：2016-08-11

申请号：US15026268

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： PATRICK MORROW ,  KIMIN JUN ,  IL-SEOK SON ,  RAJASHREE BASKARAN ,  PAUL B. FISCHER

IPC: H01L27/02 ,  H01L29/20 ,  H01L21/683 ,  H01L23/528 ,  H01L21/8258 ,  H01L29/16 ,  H01L27/085

CPC classification number: H01L27/0203 ,  H01L21/6835 ,  H01L21/8258 ,  H01L23/528 ,  H01L27/085 ,  H01L29/16 ,  H01L29/20 ,  H01L2221/68363

Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.

Abstract translation: 实施例包括一种装置，包括：第一层，包括耦合到第一接合材料的第一部分的第一半导体开关元件; 以及第二层，包括耦合到第二接合材料的第二部分的第二半导体开关元件; 其中（a）第一层在第二层之上，（b）第一部分直接连接到第二部分，和（c）第一部分的第一侧壁不均匀地锯齿。 本文描述了其它实施例。

公开(公告)号：US20160075551A1

公开(公告)日：2016-03-17

申请号：US14949470

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： RAJASHREE BASKARAN ,  CHRISTOPHER M. PELTO

IPC: B81B7/00 ,  B81B3/00

CPC classification number: B81B7/0006 ,  B81B3/0021 ,  B81B7/02 ,  B81C1/00246 ,  B81C2203/0771 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L29/84 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.

Abstract translation: 一种集成电路器件，其包括单个半导体衬底，形成在单个半导体衬底的前侧上的器件层，形成在单个半导体衬底的背面上的再分配层，形成在单个半导体衬底内的贯通硅通孔（TSV） 其被电耦合到器件层和再分配层，形成在单个半导体衬底的背面上的逻辑存储器接口（LMI），该逻辑存储器接口电耦合到再分配层;以及MEMS器件，其形成在 电耦合到再分布层的单个半导体衬底。