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公开(公告)号：US20240270566A1
公开(公告)日：2024-08-15
申请号：US18022145
申请日：2022-03-31
发明人： Hao YAN , Yulin FENG , Yue LI , Chuncheng CHE
CPC分类号： B81B7/0006 , B81C99/00 , H05K1/0306 , H05K1/115 , H05K1/181 , B81B2201/014 , B81B2203/0118 , H05K2201/10053 , H05K2201/1006
摘要： An electronic device includes a substrate having a first surface and a second surface opposite to each other in a thickness direction of the substrate, wherein the substrate has first and second connection vias which penetrate through the substrate in the thickness direction of the substrate, and first and second conductive pillars are respectively in the first connection via and the second connection via; a switch on the first surface of the substrate and comprising first and second signal electrodes, wherein the first signal electrode is electrically coupled to a first terminal of the first conductive pillar, and the second signal electrode is electrically coupled to a first terminal of the second conductive pillar; and a filter on the second surface of the substrate.
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公开(公告)号：US12051621B2
公开(公告)日：2024-07-30
申请号：US17825405
申请日：2022-05-26
IPC分类号： H01L21/768 , B24B37/04 , B81B7/00 , B81C1/00 , C23F3/00 , H01L21/306 , H01L21/311 , H01L21/321 , H01L21/3213 , H01L23/00 , C23F1/18 , H01L23/522 , H01L25/065
CPC分类号： H01L21/76868 , B24B37/042 , B81B7/0006 , B81C1/00095 , C23F3/00 , H01L21/30625 , H01L21/31111 , H01L21/3212 , H01L21/32134 , H01L21/32135 , H01L21/7684 , H01L21/76883 , H01L24/80 , H01L24/81 , C23F1/18 , H01L21/76898 , H01L23/5226 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/16145 , H01L2224/16225 , H01L2224/80031 , H01L2224/80895 , H01L2225/06506 , H01L2225/06524 , H01L2924/14 , H01L2924/1433 , H01L2924/14 , H01L2924/00012 , H01L2924/1433 , H01L2924/00012 , H01L2224/13147 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014
摘要： Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
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公开(公告)号：US20240124298A1
公开(公告)日：2024-04-18
申请号：US18152511
申请日：2023-01-10
发明人： Yun-Chung Wu , Jhao-Yi Wang , Hao Chun Yang , Pei-Wei Lee , Wen-Hsiung Lu
CPC分类号： B81C1/00095 , B81B7/0006 , B81B2207/07
摘要： Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.
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公开(公告)号：US20240083743A1
公开(公告)日：2024-03-14
申请号：US17942193
申请日：2022-09-12
发明人： RAKESH CHAND , RAMACHANDRAMURTHY PRADEEP YELEHANKA , Sock Kuan Soo , Poh Liang Yap , GUOFU ZHOU
IPC分类号： B81B7/00 , B81C1/00 , G01C19/5769 , G01P15/08
CPC分类号： B81B7/0041 , B81B7/0006 , B81C1/00293 , G01C19/5769 , G01P15/0802 , B81B2201/0235 , B81B2201/0242
摘要： A microelectromechanical systems (MEMS) package includes a first MEMS package and a second MEMS package laterally spaced apart from the first MEMS package. The first MEMS package includes a first device substrate including a first MEMS device, a first cap substrate bonded to the first device substrate, where the first cap substrate encloses a first cavity and a vent hole connected to the first cavity. A first sealing layer is filled in the vent hole, where the first sealing layer is disposed between the first device substrate and the first cap substrate. The second MEMS package includes a second device substrate including a second MEMS device and a second cap substrate. The second cap substrate is bonded to the second device substrate and encloses a second cavity. The first cavity has a first pressure, and the second cavity have a second pressure different from the first pressure.
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公开(公告)号：US20230391609A1
公开(公告)日：2023-12-07
申请号：US17805436
申请日：2022-06-03
发明人： Muir Kumph , Vivekananda P. Adiga
CPC分类号： B81B7/0006 , H01L39/22 , B81C1/00626 , B81B2207/015
摘要： A microelectromechanical system (MEMS) device and method of fabrication are provided. The MEMS devices includes a silicon substrate. The silicon substrate includes a top surface. An interconnect is machined from the silicon substrate. The interconnect includes at a spring body that has least two spring arms. Each spring arm includes a first end distal from a center of the interconnect, a second end proximate the center of the interconnect, and a single turn of a constant curvature. Each spring arm is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.
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公开(公告)号：US11776893B2
公开(公告)日：2023-10-03
申请号：US16624045
申请日：2018-06-19
发明人： Daniel S. Gianola , Gyuseok Kim
CPC分类号： H01L23/49866 , B81B7/0006 , C22C9/00 , C23C14/205 , H01B1/026 , H01L21/4846 , H01L23/145 , H01L23/4985
摘要： Metallic alloy interconnects (which can comprise copper) with low electrical resistivity and methods for making the same are disclosed. The electrical resistivity of thin film copper alloys was reduced by 36% with niobium solute and by 51% with iron solute compared to pure copper counterpart in dilute solute regimes (0-1.5 atomic %). The fabrication method is operated at room temperature, and does not require a high temperature annealing step.
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7.发明公开公开(公告)号：US20230302495A1
公开(公告)日：2023-09-28
申请号：US17993899
申请日：2022-11-24
CPC分类号： B06B1/0292 , B81B7/0006 , B81C1/00238 , B81B2201/0271 , B81B2203/0127 , B81B2203/04 , B81B2207/03 , B81B2207/07 , B81B2207/012 , B81C2201/0104 , B81C2203/036 , B81C2203/0792
摘要： The present invention provides a new architecture of system-on-chip ultrasonic transducer array. It is based on fusion bond of two active wafers which have prefabricated CMOS integrated circuits and CMUT structures; precise thin-down of one wafer to form CMUT monocrystalline silicon membrane; and then to vertically connect CMUT array to CMOS IC layers underneath. This architecture can realize a high-density CMUT array with multiple layers of CMOS devices, such as all supporting CMOS ICs, to achieve a SOC solution. The present invention further provides a manufacturing method for above-mentioned SOC CMUT approach, and this manufacturing process can be realized in both 8 inch and 12-inch wafer manufacturing fabs. The disclosed manufacturing processes are more compatible with existing CMOS process flow, more cost-competitive for mass production.
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公开(公告)号：US11667517B2
公开(公告)日：2023-06-06
申请号：US16908243
申请日：2020-06-22
发明人： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC分类号： B81B7/0006 , B81B7/0051 , B81C1/00246 , B81B2201/0257 , B81B2201/0264 , B81B2201/0271 , B81C2201/0132 , B81C2201/0133 , B81C2201/0176 , B81C2201/0181 , B81C2201/112 , B81C2203/0714 , B81C2203/0735
摘要： Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
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公开(公告)号：US20190016591A1
公开(公告)日：2019-01-17
申请号：US16137914
申请日：2018-09-21
发明人： Te-Huang Chiu , Weng-Yi Chen , Kuan-Yu Wang
CPC分类号： B81C1/00246 , B81B7/0006 , B81B2201/0214 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81B2203/0384 , B81B2203/0392 , B81B2203/04 , B81C1/00428 , B81C2201/014 , B81C2203/0735 , B81C2203/0771
摘要： A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
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10.发明申请公开(公告)号：US20180130795A1
公开(公告)日：2018-05-10
申请号：US15865774
申请日：2018-01-09
IPC分类号： H01L27/06 , H01L27/092 , A61B8/00 , B06B1/02 , B81B3/00 , H01L23/528 , H01L23/522 , H01L21/8238 , H01L21/768 , H01L21/56 , H01L21/3213 , B81C1/00 , B81B7/00
CPC分类号： H01L27/0617 , A61B8/00 , A61B8/4494 , B06B1/02 , B06B1/0292 , B06B2201/51 , B81B3/0021 , B81B7/0006 , B81B2201/0271 , B81C1/00158 , B81C1/00246 , B81C2203/0735 , B81C2203/0771 , H01L21/32134 , H01L21/56 , H01L21/768 , H01L21/76838 , H01L21/823871 , H01L23/5226 , H01L23/528 , H01L27/0688 , H01L27/092 , H01L2224/16225
摘要： Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.
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