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公开(公告)号:US20230420511A1
公开(公告)日:2023-12-28
申请号:US17850623
申请日:2022-06-27
Applicant: Intel Corporation
Inventor: Carl H. NAYLOR , Kirby MAXEY , Kevin P. O'BRIEN , Chelsey DOROW , Sudarat LEE , Ashish Verma PENUMATCHA , Uygar E. AVCI , Matthew V. METZ , Scott B. CLENDENNING , Chia-Ching LIN , Carly ROGAN , Arnab SEN GUPTA
IPC: H01L29/06 , H01L29/778 , H01L29/786 , H01L29/18 , H01L21/02
CPC classification number: H01L29/0673 , H01L29/778 , H01L29/78696 , H01L21/02568 , H01L21/02645 , H01L21/02598 , H01L21/02485 , H01L29/18
Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.
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2.
公开(公告)号:US20230420510A1
公开(公告)日:2023-12-28
申请号:US17850078
申请日:2022-06-27
Applicant: Intel Corporation
Inventor: Carl H. NAYLOR , Kirby MAXEY , Kevin P. O'BRIEN , Chelsey DOROW , Sudarat LEE , Ashish Verma PENUMATCHA , Uygar E. AVCI , Matthew V. METZ , Scott B. CLENDENNING , Jiun-Ruey CHEN , Chia-Ching LIN , Carly ROGAN
IPC: H01L29/06 , H01L29/778 , H01L29/786 , H01L29/18 , H01L21/02
CPC classification number: H01L29/0673 , H01L29/778 , H01L29/78696 , H01L29/18 , H01L21/02499 , H01L21/02568 , H01L21/02485
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.
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