公开(公告)号：US20230154539A1

公开(公告)日：2023-05-18

申请号：US17528892

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Christian Mion ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Xin Sun ,  Kristopher Gaewsky

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3459 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/56

Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

公开(公告)号：US12243590B2

公开(公告)日：2025-03-04

申请号：US17528892

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Christian Mion ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Xin Sun ,  Kristopher Gaewsky

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.