公开(公告)号：US20220199458A1

公开(公告)日：2022-06-23

申请号：US17127860

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Michael Makowski ,  Sudipto Naskar ,  Ryan Pearce ,  Nita Chandrasekhar ,  Minyoung Lee ,  Christopher Parker

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.

公开(公告)号：US12176408B2

公开(公告)日：2024-12-24

申请号：US17131467

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Willy Rachmady ,  Hsin-Fen Li ,  Christopher Parker ,  Prashant Wadhwa ,  Tahir Ghani ,  Mohammad Hasan ,  Jianqiang Lin

IPC: H01L29/423 ,  B82Y10/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.

公开(公告)号：US12087614B2

公开(公告)日：2024-09-10

申请号：US17127860

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Michael Makowski ,  Sudipto Naskar ,  Ryan Pearce ,  Nita Chandrasekhar ,  Minyoung Lee ,  Christopher Parker

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.

公开(公告)号：US20220199797A1

公开(公告)日：2022-06-23

申请号：US17131467

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Willy Rachmady ,  Hsin-Fen Li ,  Christopher Parker ,  Prashant Wadhwa ,  Tahir Ghani ,  Mohammad Hasan ,  Jianqiang Lin

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L27/088

Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.