公开(公告)号：US20220285278A1

公开(公告)日：2022-09-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Oscar OJEDA ,  Arnab ROY ,  Vahidreza PARICHEHREH ,  Leonel R. ARANA ,  Chung Kwang TAN ,  Robert A. MAY

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20190355647A1

公开(公告)日：2019-11-21

申请号：US16527961

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L21/027 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20190206767A1

公开(公告)日：2019-07-04

申请号：US15859332

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/027

CPC classification number: H01L23/485 ,  H01L21/0275 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/02 ,  H01L2223/54426 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02372

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.