公开(公告)号：US20220285278A1

公开(公告)日：2022-09-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Oscar OJEDA ,  Arnab ROY ,  Vahidreza PARICHEHREH ,  Leonel R. ARANA ,  Chung Kwang TAN ,  Robert A. MAY

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：US20200258800A1

公开(公告)日：2020-08-13

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy ECTON ,  Oscar OJEDA ,  Leonel ARANA ,  Suddhasattwa NAD ,  Robert MAY ,  Hiroki TANAKA ,  Brandon C. MARIN

IPC: H01L23/31 ,  H05K1/02 ,  H05K3/06 ,  H01L21/283

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.