公开(公告)号：US20190007310A1

公开(公告)日：2019-01-03

申请号：US15639393

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： DEBENDRA DAS SHARMA ,  MICHELLE C. JEN ,  MARK S. MYERS ,  DON SOLTIS ,  RAMACHARAN SUNDARARAMAN ,  STEPHEN R. VAN DOREN ,  MAHESH WAGH

IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US20170115716A1

公开(公告)日：2017-04-27

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： ANKUSH VARMA ,  KRISHNAKANTH V. SISTLA ,  MARTIN T. ROWLAND ,  CHRIS POIRIER ,  ERIC J. DEHAEMER ,  AVINASH N. ANANTHAKRISHNAN ,  JEREMY J. SHRALL ,  XIUTING C. MAN ,  STEPHEN H. GUNTHER ,  KRISHNA K. RANGAN ,  DEVADATTA V. BODAS ,  DON SOLTIS ,  HANG T. NGUYEN ,  CYPRIAN W. WOO ,  THI DANG

IPC: G06F1/28 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/28 ,  G06F1/3206 ,  Y02D10/152

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.