公开(公告)号：US20170285717A1

公开(公告)日：2017-10-05

申请号：US15087095

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： DEVADATTA V. BODAS ,  MURALIDHAR RAJAPPA ,  JUSTIN J. SONG ,  ANDY HOFFMAN

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3228 ,  Y02D10/126

Abstract: A system with improved power performance for task executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.

公开(公告)号：US20170115716A1

公开(公告)日：2017-04-27

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： ANKUSH VARMA ,  KRISHNAKANTH V. SISTLA ,  MARTIN T. ROWLAND ,  CHRIS POIRIER ,  ERIC J. DEHAEMER ,  AVINASH N. ANANTHAKRISHNAN ,  JEREMY J. SHRALL ,  XIUTING C. MAN ,  STEPHEN H. GUNTHER ,  KRISHNA K. RANGAN ,  DEVADATTA V. BODAS ,  DON SOLTIS ,  HANG T. NGUYEN ,  CYPRIAN W. WOO ,  THI DANG

IPC: G06F1/28 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/28 ,  G06F1/3206 ,  Y02D10/152

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.