公开(公告)号：US20200264996A1

公开(公告)日：2020-08-20

申请号：US16868603

申请日：2020-05-07

Applicant: Intel Corporation

Inventor： XIUTING C. MAN ,  JEREMY J. SHRALL ,  DEEPAK GANAPATHY ,  DORIT SHAPIRA

IPC: G06F13/24 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3296

Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

公开(公告)号：US20180095913A1

公开(公告)日：2018-04-05

申请号：US15281472

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： XIUTING C. MAN ,  JEREMY J. SHRALL ,  DEEPAK GANAPATHY ,  DORIT SHAPIRA

IPC: G06F13/24 ,  G06F1/32 ,  G06F1/20

CPC classification number: G06F13/24 ,  G06F1/206 ,  G06F1/3296 ,  Y02D10/14

Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

公开(公告)号：US20180095514A1

公开(公告)日：2018-04-05

申请号：US15281299

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： XIUTING C. MAN ,  AMIR ALI RADJAI ,  JEREMY J. SHRALL

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625 ,  G06F1/305

Abstract: In an embodiment, a processor includes a first power rail, a first component coupled to the first power rail, and a compensation control unit. The compensation control unit is to: detect a request to change a voltage level of the first power rail by a first voltage change amount; in response to detecting the request, determine that the first voltage change amount exceeds a first threshold level associated with the first component; and in response to determining that the first voltage change amount exceeds the first threshold level, initiate a first compensation action prior to changing the voltage level of the first power rail. Other embodiments are described and claimed.

公开(公告)号：US20170372771A1

公开(公告)日：2017-12-28

申请号：US15496483

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： XIUTING C. MAN ,  STANLEY S. KULICK

IPC: G11C11/406 ,  G06F15/78

CPC classification number: G11C11/40626 ,  G06F15/786 ,  G11C11/40615

Abstract: Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.

公开(公告)号：US20170115716A1

公开(公告)日：2017-04-27

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： ANKUSH VARMA ,  KRISHNAKANTH V. SISTLA ,  MARTIN T. ROWLAND ,  CHRIS POIRIER ,  ERIC J. DEHAEMER ,  AVINASH N. ANANTHAKRISHNAN ,  JEREMY J. SHRALL ,  XIUTING C. MAN ,  STEPHEN H. GUNTHER ,  KRISHNA K. RANGAN ,  DEVADATTA V. BODAS ,  DON SOLTIS ,  HANG T. NGUYEN ,  CYPRIAN W. WOO ,  THI DANG

IPC: G06F1/28 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/28 ,  G06F1/3206 ,  Y02D10/152

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.