公开(公告)号：US09614060B2

公开(公告)日：2017-04-04

申请号：US15173890

申请日：2016-06-06

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

公开(公告)号：US20150221744A1

公开(公告)日：2015-08-06

申请号：US14688647

申请日：2015-04-16

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

Abstract translation: 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当在源结构和/或漏极结构的制造中使用的材料易于被用于去除牺牲物的过程被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和/或排出结构 材料，即选择性地低至源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源极结构和/或漏极结构形成的触点之间的电位短路。

公开(公告)号：US20160284821A1

公开(公告)日：2016-09-29

申请号：US15173890

申请日：2016-06-06

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

公开(公告)号：US09385221B2

公开(公告)日：2016-07-05

申请号：US14688647

申请日：2015-04-16

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.