公开(公告)号：US10115822B2

公开(公告)日：2018-10-30

申请号：US14909981

申请日：2013-09-26

申请人： INTEL CORPORATION

发明人： Rafael Rios ,  Roza Kotlyar ,  Kelin Kuhn

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/285 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.

公开(公告)号：US09947805B2

公开(公告)日：2018-04-17

申请号：US15151381

申请日：2016-05-10

申请人： Intel Corporation

发明人： Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

IPC分类号： H01H51/22 ,  H01L29/84 ,  H01H59/00 ,  B82Y10/00 ,  H01H1/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01H9/02

CPC分类号： H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

公开(公告)号：US09614060B2

公开(公告)日：2017-04-04

申请号：US15173890

申请日：2016-06-06

申请人： Intel Corporation

发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

公开(公告)号：US10121861B2

公开(公告)日：2018-11-06

申请号：US13996850

申请日：2013-03-15

申请人： Intel Corporation

发明人： Seung Hoon Sung ,  Seiyon Kim ,  Kelin Kuhn ,  Willy Rachmady ,  Jack Kavalieros

IPC分类号： H01L29/06 ,  H01L29/10 ,  B41F3/46 ,  B41F17/08 ,  B41N10/04 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78

摘要： A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

公开(公告)号：US09825130B2

公开(公告)日：2017-11-21

申请号：US13996845

申请日：2013-03-14

申请人： Intel Corporation

发明人： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

IPC分类号： H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/16 ,  H01L29/78

CPC分类号： H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.

公开(公告)号：US20150221744A1

公开(公告)日：2015-08-06

申请号：US14688647

申请日：2015-04-16

申请人： Intel Corporation

发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

摘要翻译： 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当在源结构和/或漏极结构的制造中使用的材料易于被用于去除牺牲物的过程被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和/或排出结构 材料，即选择性地低至源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源极结构和/或漏极结构形成的触点之间的电位短路。

公开(公告)号：US20160284821A1

公开(公告)日：2016-09-29

申请号：US15173890

申请日：2016-06-06

申请人： Intel Corporation

发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

公开(公告)号：US09385221B2

公开(公告)日：2016-07-05

申请号：US14688647

申请日：2015-04-16

申请人： Intel Corporation

发明人： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

CPC分类号： H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.

公开(公告)号：US20150129830A1

公开(公告)日：2015-05-14

申请号：US13996850

申请日：2013-03-15

申请人： INTEL CORPORATION

发明人： Seung Hoon Sung ,  Kelin Kuhn ,  Seiyon Kim ,  Jack Kavalieros ,  Willy Rachmady

IPC分类号： H01L29/10 ,  H01L21/033 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC分类号： B41N10/04 ,  B41F3/46 ,  B41F17/08 ,  B41N2210/04 ,  B41N2210/14 ,  H01L21/0332 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  Y10T156/10

摘要： A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

摘要翻译： 本描述的纳米线器件可以在制造至少一个纳米线晶体管期间结合至少一个硬掩模来产生，以便有助于保护最上面的通道纳米线不受制造工艺（例如使用的那些）造成的损伤 在替代金属栅极工艺和/或纳米线释放工艺中。 使用至少一个硬掩模可能导致多层纳米线晶体管中基本上无损的最上通道纳米线，这可以提高通道纳米线的均匀性和整个多层纳米线晶体管的可靠性。