公开(公告)号：US20160308032A1

公开(公告)日：2016-10-20

申请号：US15037644

申请日：2013-12-23

申请人： INTEL CORPORATION

发明人： Glenn A. GLASS ,  Anand s. MURTHY ,  Daniel B. AUBERTINE ,  Subhash M. JOSHI

IPC分类号： H01L29/66 ,  H01L29/04 ,  H01L21/306 ,  H01L21/304 ,  H01L29/78 ,  H01L27/105

CPC分类号： H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

摘要： Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

摘要翻译： 可以通过用于尺寸雕刻的射频（RF）等离子体和/或热处理来修改晶体管鳍元件（例如，鳍或三栅极）。 蚀刻的，变薄的翅片可以通过首先形成较宽的单晶翅片形成，并且在较宽翅片之间沉积沟槽氧化物材料之后，使用第二蚀刻蚀刻较宽的翅片以形成具有未损坏的顶部和侧壁的较窄的单晶翅片，用于外延生长活性 通道材料。 第二蚀刻可以去除顶表面和较宽翅片的侧壁之间的1nm和15nm之间的厚度。 它可以使用（1）使用低离子能量等离子体处理的氯或氟基化学物质去除厚度，或者（2）低温热处理，其不会通过能量离子轰击，氧化或留下蚀刻残留物而损坏翅片，这可能会破坏 外延生长质量的第二种材料。

公开(公告)号：US20170222035A1

公开(公告)日：2017-08-03

申请号：US15487272

申请日：2017-04-13

申请人： Intel Corporation

发明人： Glenn A. GLASS ,  Anand S. MURTHY ,  Daniel B. AUBERTINE ,  Subhash M. JOSHI

IPC分类号： H01L29/78 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66 ,  H01L29/04

CPC分类号： H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

摘要： Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

公开(公告)号：US20220028747A1

公开(公告)日：2022-01-27

申请号：US17495696

申请日：2021-10-06

申请人： Intel Corporation

发明人： Glenn A. GLASS ,  Daniel B. AUBERTINE ,  Anand S. MURTHY ,  Gaurav THAREJA ,  Tahir GHANI

IPC分类号： H01L21/8238 ,  H01L29/10 ,  H01L21/8258

摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20190006508A1

公开(公告)日：2019-01-03

申请号：US15993535

申请日：2018-05-30

申请人： Intel Corporation

发明人： Glenn A. GLASS ,  Anand S. MURTHY ,  Daniel B. AUBERTINE ,  Subhash M. JOSHI

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/304 ,  H01L27/105 ,  H01L27/088 ,  H01L21/306 ,  H01L29/04

CPC分类号： H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

摘要： Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.