公开(公告)号：US20240145592A1

公开(公告)日：2024-05-02

申请号：US18407007

申请日：2024-01-08

Applicant: Intel Corporation

Inventor： Anand S. MURTHY ,  Daniel Boune AUBERTINE ,  Tahir GHANI ,  Abhijit Jayant PETHE

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7834 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L21/28079 ,  H01L29/66545

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.