公开(公告)号：US20180226407A1

公开(公告)日：2018-08-09

申请号：US15727918

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20220415894A1

公开(公告)日：2022-12-29

申请号：US17894968

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20190386007A1

公开(公告)日：2019-12-19

申请号：US16452469

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/16 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/12

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20190035790A1

公开(公告)日：2019-01-31

申请号：US16151175

申请日：2018-10-03

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/16 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20210159228A1

公开(公告)日：2021-05-27

申请号：US17142176

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20200312854A1

公开(公告)日：2020-10-01

申请号：US16900359

申请日：2020-06-12

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.