公开(公告)号：US09508660B2

公开(公告)日：2016-11-29

申请号：US14618647

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Emre Armagan ,  Rajendra C. Dias ,  Lars D. Skoglund

IPC: H01L29/06 ,  H01L23/00 ,  H01L23/31 ,  H01L23/12 ,  H01L21/304 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/563 ,  H01L23/12 ,  H01L23/3157 ,  H01L29/06 ,  H01L2224/73204

Abstract: A microelectronic die may be formed with chamfer corners for reducing stresses which can lead to delamination and/or cracking failures when such a microelectronic die is incorporated into a microelectronic package. In one embodiment, a microelectronic die may include at least one substantially planar chamfering side extending between at least two adjacent sides of a microelectronic die. In another embodiment, a microelectronic die may include at least one substantially curved or arcuate chamfering side extending between at least two adjacent sides of a microelectronic die.

Abstract translation: 可以形成具有倒角的微电子模具，用于减小当将这种微电子管芯并入微电子封装时可能导致分层和/或破裂故障的应力。 在一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上平面的倒角侧。 在另一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上弯曲或弧形的倒角侧。

公开(公告)号：US20170018525A1

公开(公告)日：2017-01-19

申请号：US15121295

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Rajendra C. Dias ,  Manish Dubey ,  Emre Armagan

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L2224/0214 ,  H01L2224/0312 ,  H01L2224/0333 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/10175 ,  H01L2224/11003 ,  H01L2224/113 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1601 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/742 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/15192 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/40102 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.

Abstract translation: 一种将集成电路（IC）附着到IC封装基板的方法包括在IC芯片的焊盘上形成焊料凸块，在IC封装基板的焊盘上形成焊料润湿突起，并将焊料凸块 的IC管芯到IC封装衬底的焊料润湿突起。

公开(公告)号：US20160233175A1

公开(公告)日：2016-08-11

申请号：US14618647

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Emre Armagan ,  Rajendra C. Dias ,  Lars D. Skoglund

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/12 ,  H01L21/304 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/563 ,  H01L23/12 ,  H01L23/3157 ,  H01L29/06 ,  H01L2224/73204

Abstract: A microelectronic die may be formed with chamfer corners for reducing stresses which can lead to delamination and/or cracking failures when such a microelectronic die is incorporated into a microelectronic package. In one embodiment, a microelectronic die may include at least one substantially planar chamfering side extending between at least two adjacent sides of a microelectronic die. In another embodiment, a microelectronic die may include at least one substantially curved or arcuate chamfering side extending between at least two adjacent sides of a microelectronic die.

Abstract translation: 可以形成具有倒角的微电子模具，用于减小当将这种微电子管芯并入微电子封装时可能导致分层和/或破裂故障的应力。 在一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上平面的倒角侧。 在另一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上弯曲或弧形的倒角侧。