公开(公告)号：US09123410B2

公开(公告)日：2015-09-01

申请号：US14011476

申请日：2013-08-27

Applicant: Intel Corporation

Inventor： Hernan A. Castro ,  Jeremy M. Hirst ,  Eric Carman

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/12

CPC classification number: G11C13/0004 ,  G11C8/12 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C2213/77

Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.

Abstract translation: 本公开涉及存储器控制器。 存储器控制器可以包括存储器控制器模块，该存储器控制器模块被配置为响应于存储器访问请求识别目标字线，所述存储器访问请求包括在交叉点存储器中的目标字线，所述存储器控制器模块还被配置为执行存储器访问操作 交叉点存储器的存储单元，存储单元耦合在目标字线和位线之间; 以及字线控制模块，被配置为浮动与所述目标字线相邻的至少一个相邻字线，所述浮动包括将所述至少一个相邻字线与第一电压源或第二电压源中的至少一个相分离。 在一些实施例中，浮动在存储器访问操作期间减少与目标字线相关联的有效电容。