公开(公告)号：US09348383B2

公开(公告)日：2016-05-24

申请号：US13783115

申请日：2013-03-01

Applicant: Intel Corporation

Inventor： Raghu Nandan Chepuri ,  Fenardi Thenus ,  Peng Zou ,  Henry W. Koertzen

IPC: G06F1/32 ,  G06F1/26 ,  H02M1/36

CPC classification number: H02M1/36 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3209 ,  H02M3/158

Abstract: Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Abstract translation: 描述了一种用于电压调节器的软启动方案。 该装置包括：第一电压调节器，用于向耦合到负载的输出节点提供调节电压，所述第一电压调节器可操作以经由旁路单元处于开环状态，所述第一电压调节器包括比较器; 以及耦合到所述第一电压调节器的第二电压调节器，其可操作以经由所述旁路单元处于闭环状态，以为所述第一电压调节器的所述比较器提供参考电压。

公开(公告)号：US10698430B2

公开(公告)日：2020-06-30

申请号：US13720050

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Fenardi Thenus ,  Peng Zou ,  Joseph T. Dibene, II

IPC: G05F1/46 ,  H02M3/158

Abstract: In some embodiments described herein, proposed schemes utilize a duty-cycle sensing technique to detect load current imbalance in each individual inductor, and then adjusts the duty cycles for the specific phases through a digital duty cycle tuner.

公开(公告)号：US20160315532A1

公开(公告)日：2016-10-27

申请号：US15152456

申请日：2016-05-11

Applicant: Intel Corporation

Inventor： Raghu Nandan Chepuri ,  Fenardi Thenus ,  Peng Zou ,  Henry W. Koertzen

IPC: H02M1/36 ,  H02M3/158

CPC classification number: H02M1/36 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3209 ,  H02M3/158

Abstract: Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Abstract translation: 描述了一种用于电压调节器的软启动方案。 该装置包括：第一电压调节器，用于向耦合到负载的输出节点提供调节电压，所述第一电压调节器可操作以经由旁路单元处于开环状态，所述第一电压调节器包括比较器; 以及耦合到所述第一电压调节器的第二电压调节器，其可操作以经由所述旁路单元处于闭环状态，以为所述第一电压调节器的所述比较器提供参考电压。

公开(公告)号：US10354611B2

公开(公告)日：2019-07-16

申请号：US15641052

申请日：2017-07-03

Applicant: Intel Corporation

Inventor： Fenardi Thenus ,  Peng Zou ,  Raghu Nandan Chepuri ,  Henry K. Koertzen

IPC: G09G5/00 ,  H02M1/00 ,  H03K5/14 ,  H03K7/06 ,  H03K7/08 ,  G06F3/041 ,  H02M3/158 ,  H03K17/284

Abstract: An apparatus comprises a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL to sample the second output with the first output and to generate a pulse-frequency modulation (PFM) output. A voltage regulator comprises mutually coupled on-die inductors for coupling to a load; a bridge coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising a comparator and a first PDL coupled to the comparator.

公开(公告)号：US09831762B2

公开(公告)日：2017-11-28

申请号：US15152456

申请日：2016-05-11

Applicant: Intel Corporation

Inventor： Raghu Nandan Chepuri ,  Fenardi Thenus ,  Peng Zou ,  Henry W. Koertzen

IPC: G06F12/14 ,  H02M1/36 ,  G06F1/26 ,  H02M3/158 ,  G06F1/32

CPC classification number: H02M1/36 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3209 ,  H02M3/158

Abstract: Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.