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公开(公告)号:US10950301B2
公开(公告)日:2021-03-16
申请号:US16320023
申请日:2016-09-30
Applicant: Intel Corporation
Inventor: Rafael Rios , Abhishek Anil Sharma , Van H. Le , Gilbert William Dewey , Jack T. Kavalieros
Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.
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公开(公告)号:US10964701B2
公开(公告)日:2021-03-30
申请号:US16480948
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Abhishek Anil Sharma , Van H. Le , Gilbert William Dewey , Rafael Rios , Jack T. Kavalieros , Yih Wang , Shriram Shivaraman
IPC: H01L27/108 , G11C11/401 , G11C11/404 , G11C11/408 , G11C11/4096 , H01L21/02 , H01L21/311 , H01L21/768 , H01L27/13 , H01L49/02 , H01L29/22 , H01L29/24 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/786 , H01L21/3105
Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
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