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公开(公告)号：US20220336633A1
公开(公告)日：2022-10-20
申请号：US17849198
申请日：2022-06-24
申请人： Intel Corporation
IPC分类号： H01L29/66 , H01L29/78 , H01L27/088 , H01L21/762 , H01L29/06 , H01L21/8234 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/165 , H01L29/417 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L23/528 , H01L27/092 , H01L27/11 , H01L49/02 , H01L29/08 , H01L29/51 , H01L27/02 , H01L21/02 , H01L29/167
摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
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公开(公告)号：US20190164814A1
公开(公告)日：2019-05-30
申请号：US15859418
申请日：2017-12-30
申请人： Intel Corporation
IPC分类号： H01L21/768 , H01L29/66 , H01L21/285 , H01L29/78 , H01L21/8234 , H01L21/762 , H01L29/06 , H01L27/088
摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A conductive interconnect line is in a trench in the ILD layer, the conductive interconnect line having a first portion and a second portion, the first portion laterally adjacent to the second portion. A dielectric plug is between and laterally adjacent to the first and second portions of the conductive interconnect line, the dielectric plug comprising a metal oxide material.
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公开(公告)号：US20210013323A1
公开(公告)日：2021-01-14
申请号：US17027568
申请日：2020-09-21
申请人： Intel Corporation
IPC分类号： H01L29/66 , H01L29/78 , H01L27/088 , H01L21/762 , H01L29/06 , H01L21/8234 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/165 , H01L29/417 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L23/528 , H01L27/092 , H01L27/11 , H01L49/02 , H01L29/08 , H01L29/51 , H01L27/02 , H01L21/02 , H01L29/167
摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
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