公开(公告)号：US20230097736A1

公开(公告)日：2023-03-30

申请号：US17485308

申请日：2021-09-24

申请人： Intel Corporation

发明人： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Jason PECK ,  Nafees A. KABIR ,  Sarah ATANASOV

IPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/11504

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220199807A1

公开(公告)日：2022-06-23

申请号：US17129867

申请日：2020-12-21

申请人： Intel Corporation

发明人： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. Sharma ,  Bernhard SELL ,  Chieh-Jen KU ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG ,  Jason PECK ,  Tobias BROWN-HEFT

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8234

摘要： Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed

公开(公告)号：US20230101111A1

公开(公告)日：2023-03-30

申请号：US17485317

申请日：2021-09-24

申请人： Intel Corporation

发明人： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Sarah ATANASOV ,  Jason PECK ,  Christopher M. NEUMANN

IPC分类号： H01L27/11514 ,  H01L27/11507

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220208778A1

公开(公告)日：2022-06-30

申请号：US17134281

申请日：2020-12-26

申请人： Intel Corporation

发明人： Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Jason PECK ,  Uygar E. AVCI ,  Jack T. KAVALIEROS

IPC分类号： H01L27/11514 ,  H01L27/11504 ,  H01L27/11507 ,  G11C7/18 ,  G11C8/14 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

摘要： A memory device comprises a series of alternating plate lines and an insulating material over a substrate. Two or more ferroelectric capacitors are through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel wordlines is along a second direction orthogonal to the first direction over the two or more ferroelectric capacitors. An access transistor is located over and controls the two or more ferroelectric capacitors, the access transistor incorporating a first one of the bitlines and a first one of the wordlines. The bitline comprise a first source/drain of a source/drain pair, and a second source/drain is aligned, and in contact, with a top one of the two or more ferroelectric capacitors, and the first wordline forms a gate of the access transistor.