公开(公告)号：US20230187395A1

公开(公告)日：2023-06-15

申请号：US17547745

申请日：2021-12-10

申请人： Intel Corporation

发明人： Nafees A. KABIR ,  Jeffery BIELEFELD ,  Manish CHANDHOK ,  Brennen MUELLER ,  Richard VREELAND

IPC分类号： H01L23/00

CPC分类号： H01L24/08 ,  H01L24/05 ,  H01L2224/08146 ,  H01L2224/05647 ,  H01L2224/02251 ,  H01L2224/0226

摘要： Embodiments herein relate to systems, apparatuses, or processes for hybrid bonding two dies, where at least one of the dies has a top layer to be hybrid bonded includes one or more copper pad and a top oxide layer surrounding the one or more copper pad, with another layer beneath the oxide layer that includes carbon atoms. The top oxide layer and the other carbide layer beneath may form a combination gradient layer that goes from a top of the top layer that is primarily an oxide to a bottom of the other layer that is primarily a carbide. The top oxide layer may be performed by exposing the carbide layer to a plasma treatment. Other embodiments may be described and/or claimed.

公开(公告)号：US20230102900A1

公开(公告)日：2023-03-30

申请号：US17485162

申请日：2021-09-24

申请人： Intel Corporation

发明人： Nafees A. KABIR ,  Shriram SHIVARAMAN ,  Seung Hoon SUNG ,  Uygar E. AVCI

IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L21/4763

摘要： A method of fabricating an integrated circuit structure comprises depositing an oxide insulator layer over a substrate having fins. A gate trench is formed within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench. A semiconducting oxide material is deposited to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins. A gate material is deposited to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins. An angled etch is performed to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.

公开(公告)号：US20230307514A1

公开(公告)日：2023-09-28

申请号：US17706218

申请日：2022-03-28

申请人： Intel Corporation

发明人： Joseph D'SILVA ,  Mauro J. KOBRINSKY ,  Shaun MILLS ,  Nafees A. KABIR ,  Makram ABD EL QADER ,  Leonard P. GULER

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742

摘要： Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

公开(公告)号：US20230097736A1

公开(公告)日：2023-03-30

申请号：US17485308

申请日：2021-09-24

申请人： Intel Corporation

发明人： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Jason PECK ,  Nafees A. KABIR ,  Sarah ATANASOV

IPC分类号： H01L27/11507 ,  G11C11/22 ,  H01L27/11504

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.