公开(公告)号：US10708093B2

公开(公告)日：2020-07-07

申请号：US16112391

申请日：2018-08-24

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Ji Chen

IPC: H04L25/03 ,  H04L29/06

Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuitry coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.

公开(公告)号：US20180097665A1

公开(公告)日：2018-04-05

申请号：US15282603

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Ji Chen

IPC: H04L25/03 ,  H04L29/06

CPC classification number: H04L25/03057 ,  H04L69/28

Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuity coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.

公开(公告)号：US10181969B2

公开(公告)日：2019-01-15

申请号：US15372851

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Ji Chen

IPC: H04L25/03 ,  H04B1/16 ,  H04L1/00 ,  H04L25/02 ,  H04L25/06 ,  H04B1/12

Abstract: An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.

公开(公告)号：US20180367349A1

公开(公告)日：2018-12-20

申请号：US16112391

申请日：2018-08-24

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Ji Chen

IPC: H04L25/03 ,  H04L29/06

Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuitry coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.

公开(公告)号：US10523411B2

公开(公告)日：2019-12-31

申请号：US15939795

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Ji Chen ,  Michael De Vita ,  Fulvio Spagna ,  Guluke Tong

IPC: H04L7/033 ,  G06F13/40 ,  G06F13/42 ,  H03L7/089 ,  H03L7/091

Abstract: Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase error information based on the input signal. A first circuit path provides proportional control information based on the data information and phase error information. A second circuit path provides integral control information based on the data information and phase error information. The first circuit path operates at a frequency higher than the second circuit path. The DCO generates a clock signal and controls the timing of the clock signal based on the integral control information and the proportional control information.

公开(公告)号：US10075308B2

公开(公告)日：2018-09-11

申请号：US15282603

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Ji Chen

IPC: H04L27/10 ,  H04L25/03 ,  H04L29/06

CPC classification number: H04L25/03057 ,  H04L25/03019 ,  H04L25/03885 ,  H04L69/28

Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuity coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.