公开(公告)号：US20190041594A1

公开(公告)日：2019-02-07

申请号：US15835177

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US20240418951A1

公开(公告)日：2024-12-19

申请号：US18795148

申请日：2024-08-05

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H04B10/40

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US12055777B2

公开(公告)日：2024-08-06

申请号：US17723174

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H04B10/40

CPC classification number: G02B6/43 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/14 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0655 ,  H04B10/40 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13101 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00012

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US20220244477A1

公开(公告)日：2022-08-04

申请号：US17723174

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H04B10/40

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US11327259B2

公开(公告)日：2022-05-10

申请号：US15835177

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Peng Li ,  Joel Martinez ,  Jon Long

IPC: G02B6/43 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H04B10/40

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

公开(公告)号：US11115025B2

公开(公告)日：2021-09-07

申请号：US15940864

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sergey Y. Shumarayev ,  David W. Mendel ,  Joel Martinez ,  Curt Wortman

IPC: H03K19/17736 ,  G06F13/42 ,  H04L7/033 ,  H01Q21/00 ,  H04L12/40

Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

公开(公告)号：US20190044517A1

公开(公告)日：2019-02-07

申请号：US15940864

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sergey Y. Shumarayev ,  David W. Mendel ,  Joel Martinez ,  Curt Wortman

IPC: H03K19/177 ,  H04L7/033 ,  G06F13/42

Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.