公开(公告)号：US20230307514A1

公开(公告)日：2023-09-28

申请号：US17706218

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Joseph D'SILVA ,  Mauro J. KOBRINSKY ,  Shaun MILLS ,  Nafees A. KABIR ,  Makram ABD EL QADER ,  Leonard P. GULER

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742

Abstract: Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

公开(公告)号：US20230317850A1

公开(公告)日：2023-10-05

申请号：US17710857

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Shaun MILLS ,  Ehren MANNEBACH ,  Joseph D'SILVA ,  Kalyan KOLLURU ,  Mauro J. KOBRINSKY

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7855 ,  H01L27/0886 ,  H01L21/823431

Abstract: Embodiments described herein may be related to creating a low resistance electrical path within a transistor between a front side trench connector and back side contacts and/or metal layers of the transistor. The low resistance electrical path does not go through a fin of the transistor that includes epitaxial material, but rather may go through a conductive path that does not include an epitaxial material. Embodiments may be compatible with a self-aligned back side contact architecture, which does not rely on deep via patterning. Other embodiments may be described and/or shown.