公开(公告)号：US20220415880A1

公开(公告)日：2022-12-29

申请号：US17357739

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Kalyan KOLLURU ,  Nicholas THOMSON ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Mauro KOBRINSKY ,  Patrick MORROW ,  Chung-Hsun LIN

IPC: H01L27/02

Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.

公开(公告)号：US20210193836A1

公开(公告)日：2021-06-24

申请号：US16719222

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Ayan KAR ,  Nicholas THOMSON ,  Benjamin ORR ,  Nathan JACK ,  Kalyan KOLLURU ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20240145471A1

公开(公告)日：2024-05-02

申请号：US18408223

申请日：2024-01-09

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Kalyan KOLLURU ,  Nathan JACK ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US20220415925A1

公开(公告)日：2022-12-29

申请号：US17358329

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Nicholas THOMSON ,  Kalyan KOLLURU ,  Ayan KAR ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Lin HU ,  Chung-Hsun LIN

IPC: H01L27/12 ,  H01L27/02

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

公开(公告)号：US20210305436A1

公开(公告)日：2021-09-30

申请号：US16830112

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

IPC: H01L29/93 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20240055497A1

公开(公告)日：2024-02-15

申请号：US18383370

申请日：2023-10-24

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Kalyan KOLLURU ,  Nathan JACK ,  Nicholas THOMSON ,  Ayan KAR ,  Benjamin ORR

IPC: H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220416022A1

公开(公告)日：2022-12-29

申请号：US17357767

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Nicholas THOMSON ,  Kalyan KOLLURU ,  Ayan KAR ,  Rui MA ,  Benjamin ORR ,  Nathan JACK ,  Biswajeet GUHA ,  Brian GREENE ,  Lin HU ,  Chung-Hsun LIN ,  Sabih OMAR

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/12

Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

公开(公告)号：US20220102385A1

公开(公告)日：2022-03-31

申请号：US17033418

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Avyaya JAYANTHINARASIMHAM ,  Ayan KAR ,  Benjamin ORR ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kalyan KOLLURU ,  Kevin FISCHER ,  Lin HU ,  Nathan JACK ,  Nicholas THOMSON ,  Rishabh MEHANDRU ,  Rui MA ,  Sabih OMAR

IPC: H01L27/12

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

公开(公告)号：US20240038889A1

公开(公告)日：2024-02-01

申请号：US18379554

申请日：2023-10-12

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Chung-Hsun LIN ,  Kinyip PHOA ,  Oleg GOLONZKA ,  Ayan KAR ,  Nicholas THOMSON ,  Benjamin ORR ,  Nathan JACK ,  Kalyan KOLLURU ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7831 ,  H01L29/785 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/42392

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20230317850A1

公开(公告)日：2023-10-05

申请号：US17710857

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Shaun MILLS ,  Ehren MANNEBACH ,  Joseph D'SILVA ,  Kalyan KOLLURU ,  Mauro J. KOBRINSKY

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7855 ,  H01L27/0886 ,  H01L21/823431

Abstract: Embodiments described herein may be related to creating a low resistance electrical path within a transistor between a front side trench connector and back side contacts and/or metal layers of the transistor. The low resistance electrical path does not go through a fin of the transistor that includes epitaxial material, but rather may go through a conductive path that does not include an epitaxial material. Embodiments may be compatible with a self-aligned back side contact architecture, which does not rely on deep via patterning. Other embodiments may be described and/or shown.