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公开(公告)号:US11199586B2
公开(公告)日:2021-12-14
申请号:US15837462
申请日:2017-12-11
Applicant: Intel Corporation
Inventor: Enrico D. Carrieri , John W. Kitterman , Keith A. Jones
IPC: G01R31/3185 , G01R31/317
Abstract: A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.
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公开(公告)号:US20190033375A1
公开(公告)日:2019-01-31
申请号:US15837462
申请日:2017-12-11
Applicant: Intel Corporation
Inventor: Enrico D. Carrieri , John W. Kitterman , Keith A. Jones
IPC: G01R31/3185 , G01R31/317
Abstract: A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.
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公开(公告)号:US11933843B2
公开(公告)日:2024-03-19
申请号:US17377264
申请日:2021-07-15
Applicant: Intel Corporation
Inventor: Keith A. Jones , Wai Mun Ng , Thomas A. Lyda , Subinlal Pk , Sankaran Menon , Vui Yong Liew , Kristan K. Wiseley
IPC: G01R31/317 , G01R31/3183 , G01R31/3185
CPC classification number: G01R31/31721 , G01R31/31705 , G01R31/318314 , G01R31/318533
Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.
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公开(公告)号:US09959222B2
公开(公告)日:2018-05-01
申请号:US14498474
申请日:2014-09-26
Applicant: Intel Corporation
Inventor: Huimin Chen , Keith A. Jones , John L. Baudrexl , Ronald W. Swartz , Vui Yong Liew
CPC classification number: G06F13/22 , G06F13/4054 , G06F13/4286
Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.
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公开(公告)号:US20160092381A1
公开(公告)日:2016-03-31
申请号:US14498474
申请日:2014-09-26
Applicant: Intel Corporation
Inventor: Huimin Chen , Keith A. Jones , John L. Baudrexl , Ronald W. Swartz , Vui Yong Liew
CPC classification number: G06F13/22 , G06F13/4054 , G06F13/4286
Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.
Abstract translation: 输入互连协议的第一状态。 根据协议将特定信号发送到通过链路的设备。 在第一状态期间,检测到在第一状态下接收到对特定信号的响应。 确定设备基于接收到的响应支持协议之外的配置模式。 基于响应输入配置模式。 在配置模式下发送一个或多个带内配置消息。
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