公开(公告)号：US20170371578A1

公开(公告)日：2017-12-28

申请号：US15193562

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Keqiang WU ,  Jiwei LU ,  Koichi YAMADA ,  Yong-Fong LEE

IPC: G06F3/06 ,  G06F9/46

CPC classification number: G06F9/467 ,  G06F9/528

Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

公开(公告)号：US20230085201A1

公开(公告)日：2023-03-16

申请号：US17802117

申请日：2020-03-30

Applicant: INTEL CORPORATION

Inventor： Keqiang WU ,  Zhidong YU ,  Cheng XU ,  Samuel ORTIZ ,  Weiting CHEN

IPC: G06F13/16 ,  G06F13/40

Abstract: The present disclosure provides an interconnect for a non-uniform memory architecture platform to provide remote access where data can dynamically and adaptively be compressed and decompressed at the interconnect link. A requesting interconnect link can add a delay to before transmitting requested data onto an interconnect bus, compress the data before transmission, or packetize and compress data before transmission. Likewise, a remote interconnect link can decompress request data.

公开(公告)号：US20160170438A1

公开(公告)日：2016-06-16

申请号：US14565512

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Keqiang WU ,  Jiwei Lu ,  Yong-Fong Lee

IPC: G06F1/12 ,  G06F9/30

CPC classification number: G06F9/30065 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30087 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/825 ,  G06F2201/865 ,  G06F2201/88

Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

Abstract translation: 一个实施例提供了一种装置。 该装置包括处理器，芯片组，用于存储处理的存储器和逻辑。 处理器包括一个或多个核心，并且是执行该过程。 逻辑是响应于大于检测利用阈值（UT）的平台处理器利用参数（PUP）来获取性能监视数据，至少部分地基于检测到的热功能和 /或检测到的热循环，使用二进制转换修改所识别的自旋循环，以创建经修改的处理部分，并且实现从所识别的旋转循环到修改的处理部分的重定向。

公开(公告)号：US20200319914A1

公开(公告)日：2020-10-08

申请号：US16861082

申请日：2020-04-28

Applicant: Intel Corporation

Inventor： Keqiang WU ,  Jiwei LU ,  Koichi YAMADA ,  Yong-Fong LEE

IPC: G06F9/46

Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.