公开(公告)号：US20230418655A1

公开(公告)日：2023-12-28

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/383 ,  G06F9/3004 ,  G06F9/30036

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220164218A1

公开(公告)日：2022-05-26

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20170371578A1

公开(公告)日：2017-12-28

申请号：US15193562

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Keqiang WU ,  Jiwei LU ,  Koichi YAMADA ,  Yong-Fong LEE

IPC: G06F3/06 ,  G06F9/46

CPC classification number: G06F9/467 ,  G06F9/528

Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

公开(公告)号：US20200319914A1

公开(公告)日：2020-10-08

申请号：US16861082

申请日：2020-04-28

Applicant: Intel Corporation

Inventor： Keqiang WU ,  Jiwei LU ,  Koichi YAMADA ,  Yong-Fong LEE

IPC: G06F9/46

Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.

公开(公告)号：US20160224348A1

公开(公告)日：2016-08-04

申请号：US14614264

申请日：2015-02-04

Applicant: Intel Corporation

Inventor： Jason M. AGRON ,  Polychronis XEKALAKIS ,  Paul CAPRIOLI ,  Jiwei Oliver LU ,  Koichi YAMADA

IPC: G06F9/30

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/4552 ,  G06F11/3466 ,  G06F11/36

Abstract: Methods and apparatuses relate to emulating architectural performance monitoring in a binary translation system. In one embodiment, a processor includes an architectural performance counter to maintain an architectural value associated with instruction execution, a register to store the architectural value of the architectural performance counter, binary translation logic to embed an architectural value from the architectural performance counter into a stream of translated instructions having a transactional code region and to store the architectural value into the register, and an execution unit to execute the transactional code region of the stream of translated instructions. The binary translation logic is configured to add the architectural value from the register to the architectural performance counter upon completion of the transactional code region of the stream of translated instructions. In one embodiment, a binary translation system overcomes software incompatibilities by using microarchitectural support to transparently and accurately emulate architectural performance counter behavior.

Abstract translation: 方法和装置涉及在二进制翻译系统中仿真架构性能监视。 在一个实施例中，处理器包括架构性能计数器，用于维护与指令执行相关联的架构值，用于存储架构性能计数器的体系结构值的寄存器，二进制翻译逻辑，用于将架构值从架构性能计数器嵌入到流中 的翻译指令具有事务代码区域并将结构值存储到寄存器中，以及执行单元，用于执行翻译指令流的事务代码区域。 二进制翻译逻辑被配置为在翻译指令流的事务代码区域完成时将来自寄存器的架构值添加到架构性能计数器。 在一个实施例中，二进制翻译系统通过使用微架构支持透明且准确地模拟架构性能计数器行为来克服软件不兼容性。

公开(公告)号：US20170185791A1

公开(公告)日：2017-06-29

申请号：US14998257

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Koichi YAMADA ,  Palanivelrajan SHANMUGAVELAYUTHAM ,  Chang Seok BAE

IPC: G06F21/62 ,  G06F21/55

CPC classification number: G06F21/52

Abstract: This disclosure is directed to a system for system for application program interface (API) monitoring bypass prevention. Operation of an API function may be preserved by generating a binary translation based on the API function native code. The native code may then be protected to prevent API monitoring bypassing. In one embodiment, access permission may be set to non-executable for a memory page in which the native code is stored. Attempts to execute the native code may generate exceptions triggering API monitoring. Alternatively, some or all of a body section of the native code may be replaced with at least one trap instruction that cause exceptions triggering API monitoring or engaging protective measures. Use of the trap instruction may be combined with at least one jump instruction added after a header section of the native code. Execution of the jump instruction may cause execution to be redirected to API monitoring.