公开(公告)号：US20220238451A1

公开(公告)日：2022-07-28

申请号：US17718038

申请日：2022-04-11

Applicant: Intel Corporation

Inventor： Christopher J. JEZEWSKI ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  Colin T. CARVER

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US20180211918A1

公开(公告)日：2018-07-26

申请号：US15925009

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Christopher J. JEZEWSKI ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  Colin T. CARVER

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US20220199516A1

公开(公告)日：2022-06-23

申请号：US17129852

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Ramanan V. CHEBIAM ,  Colin T. CARVER ,  Kevin Lai LIN ,  Mauro KOBRINSKY

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines above a substrate, individual ones of the conductive interconnect lines having a top and sidewalls. An etch stop layer is on the top and along an entirety of the sidewalls of the individual ones of the conductive interconnect lines.

公开(公告)号：US20210104435A1

公开(公告)日：2021-04-08

申请号：US17122939

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Il-Seok SON ,  Colin T. CARVER ,  Paul B. FISCHER ,  Patrick MORROW ,  Kimin JUN

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US20200286836A1

公开(公告)日：2020-09-10

申请号：US16881530

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Christopher J. JEZEWSKI ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  Colin T. CARVER

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US20190035677A1

公开(公告)日：2019-01-31

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Richard E. SCHENKER ,  Hui Jae YOO ,  Kevin L. LIN ,  Jasmeet S. CHAWLA ,  Stephanie A. BOJARSKI ,  Satyarth SURI ,  Colin T. CARVER ,  Sudipto NASKAR

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53271

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US20180233409A1

公开(公告)日：2018-08-16

申请号：US15753124

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Il-Seok SON ,  Colin T. CARVER ,  Paul B. FISCHER ,  Patrick MORROW ,  Kimin JUN

IPC: H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L21/306 ,  H01L21/304 ,  H01L21/84 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/304 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/84 ,  H01L21/845 ,  H01L25/0657 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.