公开(公告)号：US11955431B2

公开(公告)日：2024-04-09

申请号：US16987437

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Saravanan Sethuraman

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/552

Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

公开(公告)号：US11658159B2

公开(公告)日：2023-05-23

申请号：US17485078

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: G11C11/00 ,  H01L25/065 ,  G11C5/02 ,  G06F12/10

CPC classification number: H01L25/0657 ,  G06F12/10 ,  G11C5/025 ,  G06F2212/657 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US20220005521A1

公开(公告)日：2022-01-06

申请号：US17478040

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Chang Kian Tan

IPC: G11C11/4093

Abstract: A memory controller circuit includes a first channel circuit having a first programmable switch circuit that is programmable to provide a first request signal indicating a first data access request to a memory circuit. The first programmable switch circuit is programmable to provide a first write data signal indicating first data for storage in the memory circuit. The memory controller circuit includes a second channel circuit having a second programmable switch circuit that is programmable to provide one of the first request signal received from the first programmable switch circuit or a second request signal indicating a second data access request to the memory circuit. The second programmable switch circuit is programmable to provide one of the first write data signal received from the first programmable switch circuit or a second write data signal indicating second data for storage in the memory circuit.

公开(公告)号：US20230131938A1

公开(公告)日：2023-04-27

申请号：US18085819

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Scott Weber ,  Chang Kian Tan ,  Rajiv Kumar ,  Saravanan Sethuraman

IPC: G06F3/06

Abstract: An integrated circuit includes a buffer circuit, a memory circuit, and a controller circuit that determines if the memory circuit stores information that is valid and determines whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit. The controller circuit transmits the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information.

公开(公告)号：US20230126961A1

公开(公告)日：2023-04-27

申请号：US18089398

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Han Hua Leong ,  Chang Kian Tan ,  Ven Ci Kok ,  Saravanan Sethuraman ,  Wai Lim Kong

IPC: G06F21/60 ,  G06F21/76

Abstract: Methods and systems are provided for decrypting and/or encryption information received by and/or transmitted from an integrated circuit (IC) device input/output (I/O) interface. A decryption circuit is configurable to apply a first decryption algorithm selected from a plurality of decryption algorithms to received information. An encryption circuit is configurable to apply a first encryption algorithm selected from a plurality of encryption algorithms to transmitted information. A key wrapping circuit is configurable to wrap decryption and/or encryption keys associated with the first decryption and/or encryption algorithm. A firewall circuit is configurable to prevent unauthorized access to the wrapped decryption and/or encryption keys. The decryption and/or encryption circuits are reconfigurable to apply a second decryption algorithm and/or a second encryption algorithm to the received information and/or the transmitted information.

公开(公告)号：US20220188019A1

公开(公告)日：2022-06-16

申请号：US17688631

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Ramkumar Jayaraman ,  Saravanan Sethuraman ,  Diyanesh Babu Chinnakkonda Vidyapoornachary ,  Krishnaprasad H

IPC: G06F3/06

Abstract: A memory system includes a first set of memory devices, a second set of memory devices, and a memory controller circuit system. The memory controller circuit system groups a first one of the memory devices in each of the first and the second sets into a first virtual memory rank based on eye margins of first data signals sampled by the first virtual memory rank. The memory controller circuit system groups a second one of the memory devices in each of the first and the second sets into a second virtual memory rank based on eye margins of second data signals sampled by the second virtual memory rank. The memory controller circuit system accesses the memory devices in the first virtual memory rank separately from the memory devices in the second virtual memory rank during data access operations.

公开(公告)号：US20220013505A1

公开(公告)日：2022-01-13

申请号：US17485078

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: H01L25/065 ,  G11C5/02 ,  G06F12/10

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US20210384133A1

公开(公告)日：2021-12-09

申请号：US16987437

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Saravanan Sethuraman

IPC: H01L23/538 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

公开(公告)号：US11164847B2

公开(公告)日：2021-11-02

申请号：US16701739

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Saravanan Sethuraman ,  Tonia Morris ,  Siaw Kang Lai ,  Yee Choong Lim ,  Yu Ying Ong

IPC: G11C16/04 ,  H01L25/065 ,  G11C5/02 ,  G06F12/10

Abstract: An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

公开(公告)号：US12265723B2

公开(公告)日：2025-04-01

申请号：US17485343

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Chang Kian Tan ,  Ru Yin Ng ,  Saravanan Sethuraman ,  Kuljit S. Bains

IPC: G06F3/06

Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.