公开(公告)号：US20190050265A1

公开(公告)日：2019-02-14

申请号：US16146845

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Divya Vijayaraghavan ,  Denica Larsen ,  Kooi Chi Ooi ,  Lady Nataly Pinilla Pico ,  Min Suet Lim

IPC: G06F9/50 ,  G06N3/08 ,  G06K9/62 ,  G06F11/30 ,  G06N3/04

Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

公开(公告)号：US11030012B2

公开(公告)日：2021-06-08

申请号：US16146845

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Divya Vijayaraghavan ,  Denica Larsen ,  Kooi Chi Ooi ,  Lady Nataly Pinilla Pico ,  Min Suet Lim

IPC: G06F9/50 ,  G06N3/08 ,  G06N3/04 ,  G06F11/30 ,  G06K9/62

Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

公开(公告)号：US20180188960A1

公开(公告)日：2018-07-05

申请号：US15394933

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Lady Nataly Pinilla Pico

IPC: G06F3/06 ,  G06F12/121

Abstract: In one embodiment, an apparatus comprises a plurality of memory partitions, each memory partition comprising an array of 3D crosspoint memory, and a storage device controller comprising a memory comprising memory cells to store addresses of replacement memory partitions and addresses of unusable memory partitions and a partition address translation engine coupled to the memory, the partition address translation engine comprising logic to determine whether to redirect a memory access command received from a host computing device to a replacement memory partition based on the contents of the memory.

公开(公告)号：US11710029B2

公开(公告)日：2023-07-25

申请号：US16147037

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kooi Chi Ooi ,  Min Suet Lim ,  Denica Larsen ,  Lady Nataly Pinilla Pico ,  Divya Vijayaraghavan

IPC: G06N3/045 ,  G06N3/08 ,  G06N5/04 ,  G06N3/063 ,  G06F15/78 ,  G06F1/16 ,  G06N20/00 ,  G06F16/00 ,  G06N3/084 ,  G06V10/94 ,  G06F18/214 ,  G06F18/21 ,  G06F18/2413 ,  G06N3/048 ,  G06V10/764 ,  G06V10/774 ,  G06V10/776 ,  G06V10/82

CPC classification number: G06N3/063 ,  G06F1/163 ,  G06F15/7892 ,  G06F16/00 ,  G06F18/214 ,  G06F18/217 ,  G06F18/24143 ,  G06N3/045 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084 ,  G06N5/04 ,  G06N20/00 ,  G06V10/764 ,  G06V10/774 ,  G06V10/776 ,  G06V10/82 ,  G06V10/955

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.

公开(公告)号：US20210406085A1

公开(公告)日：2021-12-30

申请号：US17317679

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Divya Vijayaraghavan ,  Denica Larsen ,  Kooi Chi Ooi ,  Lady Nataly Pinilla Pico ,  Min Suet Lim

IPC: G06F9/50 ,  G06N3/08 ,  G06N3/04 ,  G06F11/30 ,  G06K9/62

Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

公开(公告)号：US10802742B2

公开(公告)日：2020-10-13

申请号：US16152460

申请日：2018-10-05

Applicant: Intel Corporation

Inventor： Rezaul Haque ,  Lady Nataly Pinilla Pico

IPC: G06F3/06 ,  G06F1/3234 ,  G11C5/14 ,  G11C7/10 ,  G11C7/22

Abstract: The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.

公开(公告)号：US20230281075A1

公开(公告)日：2023-09-07

申请号：US18171116

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Wei Yee Koay ,  Rita H. Wouhaybi ,  Melissa M. Ortiz ,  Shahrnaz Azizi ,  Gayathri Jeganmohan ,  Lady Nataly Pinilla Pico

IPC: G06F11/07 ,  G07C5/08 ,  G06F11/22 ,  G06F11/00 ,  G06F11/20

CPC classification number: G06F11/0793 ,  G07C5/0808 ,  G06F11/0739 ,  G06F11/2289 ,  G06F11/00 ,  G06F11/20 ,  G07C5/008

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

公开(公告)号：US11586492B2

公开(公告)日：2023-02-21

申请号：US17479511

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Wei Yee Koay ,  Rita H. Wouhaybi ,  Melissa M. Ortiz ,  Shahrnaz Azizi ,  Gayathri Jeganmohan ,  Lady Nataly Pinilla Pico

IPC: G06F11/00 ,  G06F11/07 ,  G07C5/08 ,  G06F11/22 ,  G06F11/20 ,  G07C5/00 ,  G05D1/00

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

公开(公告)号：US11104529B2

公开(公告)日：2021-08-31

申请号：US16140479

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Lady Nataly Pinilla Pico ,  Melissa M. Ortiz ,  Gayathri Jeganmohan ,  Wei Yee Koay ,  Shahrnaz Azizi ,  Rita H. Wouhaybi

IPC: G05D1/00 ,  B65G67/04 ,  G05D1/02

Abstract: Embodiments include apparatuses, methods, and systems to provide an automated loading device to a computer assisted or autonomous driving (CA/AD) vehicle. A loading service control device is to initiate a loading service to load one or more items into a storage space of a CA/AD vehicle, using an automated loading device. A CA/AD vehicle is to move to a loading area at an appointed time. A mechanical loading unit of an automated loading device is to place one or more items into a storage space of a CA/AD vehicle. A user device is to receive an input from a user, where the input includes information to generate a request to a loading service control device to load one or more items into a storage space of a CA/AD vehicle using an automated loading device. Other embodiments may also be described and claimed.

公开(公告)号：US10725933B2

公开(公告)日：2020-07-28

申请号：US15394933

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Lady Nataly Pinilla Pico

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/121 ,  G06F3/06

Abstract: In one embodiment, an apparatus comprises a plurality of memory partitions, each memory partition comprising an array of 3D crosspoint memory, and a storage device controller comprising a memory comprising memory cells to store addresses of replacement memory partitions and addresses of unusable memory partitions and a partition address translation engine coupled to the memory, the partition address translation engine comprising logic to determine whether to redirect a memory access command received from a host computing device to a replacement memory partition based on the contents of the memory.