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    APPARATUS AND METHOD FOR REDUCED PRECISION BOUNDING VOLUME HIERARCHY CONSTRUCTION
    2.
    发明申请
    APPARATUS AND METHOD FOR REDUCED PRECISION BOUNDING VOLUME HIERARCHY CONSTRUCTION 有权

    公开(公告)号：US20220270319A1

    公开(公告)日：2022-08-25

    申请号：US17735902

    申请日：2022-05-03

    Applicant: Intel Corporation

    Inventor： MICHAEL DOYLE ,  KARTHIK VAIDYANATHAN

    IPC: G06T15/10 ,  G06T1/60 ,  G06T9/00 ,  G06T15/06

    Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

    APPARATUS AND METHOD FOR REDUCED PRECISION BOUNDING VOLUME HIERARCHY CONSTRUCTION
    5.
    发明申请
    APPARATUS AND METHOD FOR REDUCED PRECISION BOUNDING VOLUME HIERARCHY CONSTRUCTION 审中-公开

    公开(公告)号：US20200320776A1

    公开(公告)日：2020-10-08

    申请号：US16746636

    申请日：2020-01-17

    Applicant: INTEL CORPORATION

    Inventor： MICHAEL DOYLE ,  KARTHIK VAIDYANATHAN

    IPC: G06T15/10 ,  G06T9/00 ,  G06T1/60 ,  G06T15/06

    Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

    APPARATUS AND METHOD FOR A HIERARCHICAL BEAM TRACER
    6.
    发明申请
    APPARATUS AND METHOD FOR A HIERARCHICAL BEAM TRACER 审中-公开

    公开(公告)号：US20200211263A1

    公开(公告)日：2020-07-02

    申请号：US16235906

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： SCOTT JANUS ,  PRASOONKUMAR SURTI ,  KARTHIK VAIDYANATHAN ,  ALEXEY SUPIKOV ,  GABOR LIKTOR ,  CARSTEN BENTHIN ,  PHILIP LAWS ,  MICHAEL DOYLE

    IPC: G06T15/06 ,  G06T17/00 ,  G06T15/00 ,  G06T1/60

    Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

    SPECULATIVE EXECUTION OF HIT AND INTERSECTION SHADERS ON PROGRAMMABLE RAY TRACING ARCHITECTURES
    7.
    发明申请
    SPECULATIVE EXECUTION OF HIT AND INTERSECTION SHADERS ON PROGRAMMABLE RAY TRACING ARCHITECTURES 审中-公开

    公开(公告)号：US20200211253A1

    公开(公告)日：2020-07-02

    申请号：US16236176

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： GABOR LIKTOR ,  KARTHIK VAIDYANATHAN ,  JEFFERSON AMSTUTZ ,  ATSUO KUWAHARA ,  MICHAEL DOYLE ,  TRAVIS SCHLUESSLER

    IPC: G06T15/00 ,  G06T15/06 ,  G06T1/60

    Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

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