-
公开(公告)号：US20220270319A1
公开(公告)日：2022-08-25
申请号：US17735902
申请日：2022-05-03
Applicant: Intel Corporation
Inventor： MICHAEL DOYLE , KARTHIK VAIDYANATHAN
Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.
-
公开(公告)号：US20200211268A1
公开(公告)日：2020-07-02
申请号：US16367062
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： KARTHIK VAIDYANATHAN , SVEN WOOP , CARSTEN BENTHIN
Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes; and traversal tracking circuitry to maintain a path encoding array to store path data related to the current traversal path, the path data comprising an index of a currently traversed child node; wherein the traversal/intersection circuitry is to prevent one or more subsequent rays from re-intersecting primitives from which they originated and/or avoid re-traversing the current traversal path based on the path data in the path encoding array.
-
公开(公告)号：US20230359496A1
公开(公告)日：2023-11-09
申请号：US17589689
申请日：2022-01-31
Applicant: Intel Corporation
Inventor： PAWEL MAJEWSKI , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , JOSHUA BARCZAK , VASANTH RANGANATHAN , VIKRANTH VEMULAPALLI
CPC classification number: G06F9/5027 , G06F9/4881 , G06F9/54
Abstract: Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.
-
公开(公告)号：US20200211261A1
公开(公告)日：2020-07-02
申请号：US16235744
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： SCOTT JANUS , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , GABOR LIKTOR , CARSTEN BENTHIN , PHILIP LAWS
Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.
-
公开(公告)号：US20190340812A1
公开(公告)日：2019-11-07
申请号：US15972644
申请日：2018-05-07
Applicant: Intel Corporation
Inventor： VALENTIN FUETTERLING , GABOR LIKTOR , KARTHIK VAIDYANATHAN
Abstract: A system and method for adaptive hierarchical tessellation. For example, one embodiment of a method comprises: a tessellation queue to store portions of a first image frame to be tessellated; motion vector analysis circuitry to group a plurality of sub-tiles within each of a plurality of tiles at multiple levels of granularity, wherein the sub-tiles of a first level comprise pixels and the sub-tiles of each successive level comprise tiles from a previous level, the motion vector analysis circuitry to iteratively analyze motion vectors of each group of sub-tiles at each level of granularity to determine whether the motion vectors are similar in accordance with a defined threshold, the motion vector analysis circuitry to queue tiles having sub-tiles which are determined to be dissimilar to the tessellation queue.
-
Patent Agency Ranking
公开(公告)号：US20220012934A1
公开(公告)日：2022-01-13
申请号：US17349602
申请日：2021-06-16
Applicant: Intel Corporation
Inventor： HOLGER GRUEN , KARTHIK VAIDYANATHAN
Abstract: Apparatus and method for more precise level-of-details transitions. For example one embodiment includes a graphics processor comprising: ray traversal hardware logic to traverse a ray through an acceleration structure to determine intersections between the ray and one or more object instances; and a level of detail selector to: set an instance comparison mask associated with an object instance to a first level of detail (LOD), the instance comparison mask comprising an N-bit value and one or more bits to indicate a type of comparison operation, compare a value from a ray mask with the N-bit value in accordance with the type of comparison operation to generate a comparison result, and determine whether to use the first LOD or a second LOD to render one or more pixels in accordance with the comparison result.
-
公开(公告)号：US20210201558A1
公开(公告)日：2021-07-01
申请号：US16728375
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： KAROL SZERSZEN , PRASOONKUMAR SURTI , GABOR LIKTOR , KARTHIK VAIDYANATHAN , SVEN WOOP
Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
-
公开(公告)号：US20200211252A1
公开(公告)日：2020-07-02
申请号：US16235893
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： PRASOONKUMAR SURTI , CARSTEN BENTHIN , KARTHIK VAIDYANATHAN , PHILIP LAWS , SCOTT JANUS , SVEN WOOP
Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
-
公开(公告)号：US20150379763A1
公开(公告)日：2015-12-31
申请号：US14319130
申请日：2014-06-30
Applicant: INTEL CORPORATION
Inventor： GABOR LIKTOR , MARCO SALVI , KARTHIK VAIDYANATHAN
CPC classification number: G06T15/80 , G06T1/20 , G06T15/005 , G06T15/04
Abstract: An apparatus and method for performing coarse pixel shading (CPS). For example, one embodiment of a method comprises: A method for coarse pixel shading (CPS) comprising: pre-processing a graphics mesh by creating a tangent-plane parameterization of desired vertex attributes for each vertex of the mesh; and performing rasterization of the mesh in a rasterization stage of a graphics pipeline using the tangent-plane parameterization.
Abstract translation: 一种用于执行粗略像素阴影（CPS）的设备和方法。 例如，一种方法的一个实施例包括：一种用于粗略像素着色（CPS）的方法，包括：通过为所述网格的每个顶点创建所需顶点属性的切平面参数化来预处理图形网格; 以及使用切平面参数化在图形管线的光栅化阶段中执行网格的光栅化。
-
公开(公告)号：US20210149811A1
公开(公告)日：2021-05-20
申请号：US16685224
申请日：2019-11-15
Applicant: Intel Corporation
Inventor： ABHISHEK R. APPU , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , KAROL SZERSZEN
IPC: G06F12/0884 , G06F12/0837 , H03M7/30 , G06F9/30
Abstract: An apparatus to facilitate packing compressed data is disclosed. The apparatus includes compression hardware to compress memory data into a plurality of compressed data components and packing hardware to receive the plurality of compressed data components and pack a first of the plurality of compressed data components beginning at a least significant bit (LSB) location of a compressed bit stream and pack a second of the plurality of compressed data components beginning at a most significant bit (MSB) of the compressed bit stream.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.014 seconds)
