公开(公告)号：US20220114125A1

公开(公告)日：2022-04-14

申请号：US17067365

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Anshuman THAKUR ,  Dheeraj SUBBAREDDY ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Mahesh KUMASHIKAR

IPC: G06F13/40

Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

公开(公告)号：US20240145434A1

公开(公告)日：2024-05-02

申请号：US18210847

申请日：2023-06-16

Applicant: Intel Corporation

Inventor： Mahesh KUMASHIKAR ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16

Abstract: Die configuration types are provided that may be used together with other instances of the design to create multi die modules.

公开(公告)号：US20220114121A1

公开(公告)日：2022-04-14

申请号：US17067334

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Anshuman THAKUR ,  Dheeraj SUBAREDDY ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Mahesh KUMASHIKAR ,  Sandeep SANE

IPC: G06F13/20

Abstract: A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

公开(公告)号：US20220100692A1

公开(公告)日：2022-03-31

申请号：US17033593

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Dheeraj SUBBAREDDY ,  Ankireddy NALAMALPU ,  Anshuman THAKUR ,  MD Altaf HOSSAIN ,  Mahesh KUMASHIKAR ,  Kemal AYGÜN ,  Casey THIELEN ,  Daniel KLOWDEN ,  Sandeep B. SANE

IPC: G06F13/42

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.