公开(公告)号：US20220114121A1

公开(公告)日：2022-04-14

申请号：US17067334

申请日：2020-10-09

申请人： Intel Corporation

发明人： Anshuman THAKUR ,  Dheeraj SUBAREDDY ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Mahesh KUMASHIKAR ,  Sandeep SANE

IPC分类号： G06F13/20

摘要： A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

公开(公告)号：US20220092016A1

公开(公告)日：2022-03-24

申请号：US17031823

申请日：2020-09-24

申请人： Intel Corporation

发明人： Mahesh K. KUMASHIKAR ,  Dheeraj SUBBAREDDY ,  Anshuman THAKUR ,  MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Casey G. THIELEN ,  Daniel S. KLOWDEN ,  Kevin P. MA ,  Sergey Yuryevich SHUMARAYEV ,  Sandeep SANE ,  Conor O'KEEFFE

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G11C7/10

摘要： Embodiments herein relate to systems, apparatuses, or techniques for using an optical physical layer die within a system-on-a-chip to optically couple with an optical physical layer die on another package to provide high-bandwidth memory access between the system-on-a-chip and the other package. In embodiments, the other package may be a large optically connected memory device that includes a memory controller coupled with an optical physical layer die, where the memory controller is coupled with memory. Other embodiments may be described and/or claimed.

公开(公告)号：US20190037708A1

公开(公告)日：2019-01-31

申请号：US16072367

申请日：2016-04-01

申请人： INTEL CORPORATION

发明人： Sandeep SANE ,  Timothy SWETTLEN

IPC分类号： H05K3/40 ,  H01L23/498 ,  H05K3/34

CPC分类号： H05K3/4015 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49833 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/10734

摘要： The systems and methods described herein are directed to using a plurality of interface elements (e.g., sockets) and/or stud-bump elements embedded into board substrates (e.g., a motherboard) to enable the interchange of variable configuration components (e.g., electronic components, chips, and the like) that are mounted on package substrates having ball grid arrays (BGAs). In some aspects, this interchange can be accomplished while leaving the pre-existing board substrate design and various peripheral system components of the board substrate unchanged.