公开(公告)号：US20240105802A1

公开(公告)日：2024-03-28

申请号：US17953085

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Marie CONTE ,  Charles H. WALLACE ,  Robert JOACHIM ,  Shengsi LIU ,  Saurabh ACHARYA ,  Nidhi KHANDELWAL ,  Kyle T. HORAK ,  Robert ROBINSON ,  Brandon PETERS

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78696

Abstract: Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends into but not entirely through the conductive trench contact.

公开(公告)号：US20220399373A1

公开(公告)日：2022-12-15

申请号：US17348000

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka MUNASINGHE ,  Makram ABD EL QADER ,  Marie CONTE ,  Saurabh MORARKA ,  Elliot N. TAN ,  Krishna GANESAN ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84

Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.