公开(公告)号：US20210305436A1

公开(公告)日：2021-09-30

申请号：US16830112

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

IPC: H01L29/93 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20190334034A1

公开(公告)日：2019-10-31

申请号：US16509421

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Michael JACKSON ,  Anand MURTHY ,  Glenn GLASS ,  Saurabh MORARKA ,  Chandra MOHAPATRA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US20220344519A1

公开(公告)日：2022-10-27

申请号：US17860056

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Saurabh MORARKA ,  Carlos NIEVA-LOZANO ,  Kalyan KOLLURU ,  Biswajeet GUHA ,  Chung-Hsun LIN ,  Brian GREENE ,  Tahir GHANI

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20220399445A1

公开(公告)日：2022-12-15

申请号：US17347034

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Conor P. PULS ,  Walid M. HAFEZ ,  Sairam SUBRAMANIAN ,  Justin S. SANDFORD ,  Saurabh MORARKA ,  Sean PURSEL ,  Mohammad HASAN

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

Abstract: Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

公开(公告)号：US20220399373A1

公开(公告)日：2022-12-15

申请号：US17348000

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka MUNASINGHE ,  Makram ABD EL QADER ,  Marie CONTE ,  Saurabh MORARKA ,  Elliot N. TAN ,  Krishna GANESAN ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84

Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.