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1.发明授权Dynamically adjusting power of non-core processor circuitry including buffer circuitry 有权动态调整包括缓冲电路在内的非核心处理器电路的功率公开(公告)号：US09501129B2
公开(公告)日：2016-11-22
申请号：US13780052
申请日：2013-02-28
Applicant: Intel Corporation
Inventor： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
CPC classification number: G06F1/324 , G06F13/4022 , Y02D10/126
Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。
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2.发明申请Dynamically Modifying A Power/Performance Tradeoff Based On A Processor Utilization 有权基于处理器利用率动态修改电源/性能权衡公开(公告)号：US20160266941A1
公开(公告)日：2016-09-15
申请号：US15162709
申请日：2016-05-24
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Cagdas Akturan , Avinash N. Ananthakrishnan
CPC classification number: G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有功率控制器的多核处理器，所述功率控制器具有在处理器的利用率超过阈值水平时将功率管理策略从功率偏置策略动态切换到性能偏差策略的逻辑。 因此，在低利用率下，可以实现降低的功率消耗，而在更高的利用率下，可以实现更高的性能。 描述和要求保护其他实施例。
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公开(公告)号：US09760409B2
公开(公告)日：2017-09-12
申请号：US15162709
申请日：2016-05-24
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Chelsea Akturan , Avinash N. Ananthakrishnan
CPC classification number: G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
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