公开(公告)号：US20180232024A1

公开(公告)日：2018-08-16

申请号：US15846161

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Krishnakanth Sistla ,  Martin Rowland ,  Efraim Rotem ,  Brian J. Griffith ,  Ankush Varma ,  Anupama Suryanarayanan

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/24

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

公开(公告)号：US10429912B2

公开(公告)日：2019-10-01

申请号：US15846161

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Krishnakanth Sistla ,  Martin Rowland ,  Efraim Rotem ,  Brian J. Griffith ,  Ankush Varma ,  Anupama Suryanarayanan

IPC: G06F1/26 ,  G06F1/329 ,  G06F1/3203 ,  G06F1/3234

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.