公开(公告)号：US20170083079A1

公开(公告)日：2017-03-23

申请号：US15370507

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/1626 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3243 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151 ,  Y02D10/152

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

公开(公告)号：US09513662B2

公开(公告)日：2016-12-06

申请号：US13734612

申请日：2013-01-04

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/00 ,  G06F1/16 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/1626 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3243 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151 ,  Y02D10/152

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Abstract translation: 本文描述的特定实施例可以提供一种用于管理至少一个处理器的功率的方法，该处理器包括评估与电子设备相关联的多个端口; 确定与所述端口中的至少一个相关联的特定引脚没有接收到信号; 禁用与所述电子设备相关联的静噪功能; 以及与电子设备的物理层（PHY）相关联的门控功率。

公开(公告)号：US10248183B2

公开(公告)日：2019-04-02

申请号：US15370507

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/16 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3218 ,  G06F13/42

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.