公开(公告)号：US10467010B2

公开(公告)日：2019-11-05

申请号：US14209736

申请日：2014-03-13

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Mandeep Singh

IPC: G06F9/38 ,  G06F9/30

Abstract: A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load operation and wherein the store has potential to result in a RAW violation in conjunction with the load operation. The method also comprises issuing the load operation from an instruction scheduling module. Further, the method comprises acquiring data for the load operation speculatively after the load operation has arrived at a load store queue module. Finally, the method comprises determining if an identification number associated with a last contiguous issued store with respect to the load operation is equal to or greater than the tag and gating a validation process for the load operation in response to the determination.

公开(公告)号：US20190056964A1

公开(公告)日：2019-02-21

申请号：US16166010

申请日：2018-10-19

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ankur Groen ,  Erika Gunadi ,  Mandeep Singh ,  Ravishankar Rao

IPC: G06F9/455 ,  G06F12/109 ,  G06F12/1036 ,  G06F12/1027 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

公开(公告)号：US20170337063A1

公开(公告)日：2017-11-23

申请号：US15673286

申请日：2017-08-09

Applicant: Intel Corporation

Inventor： Mohammad A. ABDALLAH ,  Mandeep Singh

IPC: G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/3834 ,  G06F9/3857

Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

公开(公告)号：US10740126B2

公开(公告)日：2020-08-11

申请号：US16166010

申请日：2018-10-19

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ankur Groen ,  Erika Gunadi ,  Mandeep Singh ,  Ravishankar Rao

IPC: G06F9/32 ,  G06F12/08 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/1036 ,  G06F9/38

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

公开(公告)号：US10713047B2

公开(公告)日：2020-07-14

申请号：US16434066

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Mandeep Singh ,  Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/0888 ,  G06F13/16

Abstract: Fast unaligned memory access. hi accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.

公开(公告)号：US10289419B2

公开(公告)日：2019-05-14

申请号：US15673286

申请日：2017-08-09

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Mandeep Singh

IPC: G06F9/38

Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

公开(公告)号：US09753734B2

公开(公告)日：2017-09-05

申请号：US15215004

申请日：2016-07-20

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Mandeep Singh

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/3834 ,  G06F9/3857

Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

公开(公告)号：US10140138B2

公开(公告)日：2018-11-27

申请号：US14216493

申请日：2014-03-17

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ankur Groen ,  Erika Gunadi ,  Mandeep Singh ,  Ravishankar Rao

IPC: G06F9/38 ,  G06F9/44 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/1036 ,  G06F9/32 ,  G06F12/109

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.