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公开(公告)号:US12131912B2
公开(公告)日:2024-10-29
申请号:US18531359
申请日:2023-12-06
Applicant: Intel Corporation
Inventor: Muralidhar S. Ambati , Ritesh Jhaveri , Moosung Kim
IPC: H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/324 , H01L29/06 , H01L29/66
CPC classification number: H01L21/3065 , H01L21/3085 , H01L21/3086 , H01L21/31116 , H01L21/324 , H01L29/0642 , H01L29/0657 , H01L29/66795
Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.
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公开(公告)号:US11417531B2
公开(公告)日:2022-08-16
申请号:US17164230
申请日:2021-02-01
Applicant: Intel Corporation
Inventor: Muralidhar S. Ambati , Ritesh Jhaveri , Moosung Kim
IPC: H01L21/3065 , H01L21/308 , H01L21/311 , H01L29/66 , H01L21/324 , H01L29/06
Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.
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公开(公告)号:US10950453B2
公开(公告)日:2021-03-16
申请号:US16836432
申请日:2020-03-31
Applicant: Intel Corporation
Inventor: Muralidhar S. Ambati , Ritesh Jhaveri , Moosung Kim
IPC: H01L21/3065 , H01L21/308 , H01L21/311 , H01L29/66 , H01L21/324 , H01L29/06
Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.
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公开(公告)号:US11875999B2
公开(公告)日:2024-01-16
申请号:US17860058
申请日:2022-07-07
Applicant: Intel Corporation
Inventor: Muralidhar S. Ambati , Ritesh Jhaveri , Moosung Kim
IPC: H01L21/3065 , H01L21/308 , H01L21/311 , H01L29/66 , H01L21/324 , H01L29/06
CPC classification number: H01L21/3065 , H01L21/3085 , H01L21/3086 , H01L21/31116 , H01L21/324 , H01L29/0642 , H01L29/0657 , H01L29/66795
Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.
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公开(公告)号:US10204794B2
公开(公告)日:2019-02-12
申请号:US15036351
申请日:2013-12-23
Applicant: Intel Corporation
Inventor: Muralidhar S. Ambati , Ritesh Jhaveri , Moosung Kim
IPC: H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/324 , H01L29/06 , H01L29/66
Abstract: Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.
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